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PDF HD74CDCF2509B Data sheet ( Hoja de datos )
| Número de pieza | HD74CDCF2509B | |
| Descripción | 140 MHz/ 0 to 85C Operation 3.3-V Phase-lock Loop Clock Driver | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HD74CDCF2509B
140 MHz, 0 to 85°C Operation
3.3-V Phase-lock Loop Clock Driver
ADE-205-224F (Z)
7th. Edition
January 2000
Description
The HD74CDCF2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the
clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The
HD74CDCF2509B operates at 3.3 V VCC and is designed to drive up to five clock loads per output.
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of the input
clock. Output signal duty cycles are adjusted to 50 percent independent of the duty cycle at the input clock.
Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the
G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the
outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the HD74CDCF2509B does not require external RC networks.
The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, HD74CDCF2509B requires a stabilization time to achieve phase lock
of the feedback signal to the reference signal. This stabilization time is required, following power up and
application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL
reference or feedback signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
Features
• Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1”
• Phase-lock loop clock distribution for synchronous DRAM applications
• External feedback (FBIN) pin is used to synchronize the outputs to the clock input
• No external RC network required
• Support spread spectrum clock (SSC) synthesizers
• Supports frequencies up to 140 MHz
• 0 to 85°C operating range
1 page  
HD74CDCF2509B
Pin Function
Pin name
CLK
FBIN
1G
2G
FBOUT
1Y(0:4)
2Y(0:3)
AVCC
AGND
VCC
GND
No. Type Description
24 I Clock input. CLK provides the clock signal to be distributed by the
HD74CDCF2509B clock driver. CLK is used to provide the
reference signal to the integrated PLL that generates the clock
output signals. CLK must have a fixed frequency and fixed phase
for the PLL to obtain phase lock. Once the circuit is powered up
and a valid CLK signal is applied, a stabilization time is required for
the PLL to phase lock the feedback signal to its reference signal.
13 I Feedback input. FBIN provides the feedback signal to the internal
PLL. FBIN must be hard-wired to FBOUT to complete the PLL.
The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
11 I Output bank enable. 1G is the output enable for outputs 1Y(0:4).
When 1G is low, outputs 1Y(0:4)are disabled to a logic-low state.
When 1G is high, all outputs 1Y(0:4) are enabled and switch at the
same frequency as CLK.
14 I Output bank enable. 2G is the output enable for outputs 2Y(0:3).
When 2G is low, outputs 2Y(0:3)are disabled to a logic low state.
When 2G is high, all outputs 2Y(0:3) are enabled and switch at the
same frequency as CLK.
12 O Feedback output. FBOUT is dedicated for external feedback. It
switches at the same frequency as CLK. When externally wired to
FBIN, FBOUT completes the feedback loop of the PLL.
3, 4, 5, 8, 9 O
Clock outputs. These outputs provide low-skew copies of CLK.
Output bank 1Y(0:4) is enabled via the 1G input. These outputs
can be disabled to a logic low state by deasserting the 1G control
input.
16, 17, 20, O
21
Clock outputs. These outputs provide low-skew copies of CLK.
Output bank 2Y(0:3) is enabled via the 2G input. These outputs
can be disabled to a logic low state by deasserting the 2G control
input.
23 Power Analog power supply. AVCC provides the power reference for the
analog circuitry. In addition, AVCC can be used to bypass the PLL
for test purposes. When AVCC is strapped to ground, PLL is
bypassed and CLK is buffered directly to the device outputs.
1 Ground Analog ground. AGND provides the ground reference for the
analog circuitry.
2, 10, 15, 22 Power Power supply
6, 7, 18,19 Ground Ground
5
5 Page 
HD74CDCF2509B
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-
safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
Europe
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Asia (Taiwan)
Asia (HongKong)
Japan
: http:semiconductor.hitachi.com/
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: http://www.has.hitachi.com.sg/grp3/sicd/index.htm
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
: http://www.hitachi.com.hk/eng/bo/grp3/index.htm
: http://www.hitachi.co.jp/Sicd/index.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
179 East Tasman Drive,
San Jose,CA 95134
Tel: <1> (408) 433-1990
Fax: <1>(408) 433-0223
Hitachi Europe GmbH
Electronic components Group
Dornacher Stra§e 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Hitachi Asia Pte. Ltd.
Hitachi Asia (Hong Kong) Ltd.
16 Collyer Quay #20-00
Group III (Electronic Components)
Hitachi Tower
7/F., North Tower, World Finance Centre,
Singapore 049318
Harbour City, Canton Road, Tsim Sha Tsui,
Tel: 535-2100
Kowloon, Hong Kong
Fax: 535-1533
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Hitachi Asia Ltd.
Telex: 40815 HITEC HX
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Copyright ' Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
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