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PDF HD74BC534A Data sheet ( Hoja de datos )

Número de pieza HD74BC534A
Descripción Octal D Type Flip Flops With 3 State Outputs
Fabricantes Hitachi Semiconductor 
Logotipo Hitachi Semiconductor Logotipo



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HD74BC534A
Octal D Type Flip Flops With 3 State Outputs
ADE-205-012 (Z)
Rev. 0
June 1993
Description
The HD74BC534A provides high drivability and operation equal to or better than high speed bipolar
standard logic IC by using Bi-CMOS process. The device features low power dissipation that is about 1/5
of high speed bipolar logic IC, when the frequency is 10 MHz. The device has eight edge triger D type flip
flop with three state outputs in a 20 pin package. Data at the D inputs meeting set up reguirements, are
transferred to the Q outputs on positive going transitions of the clock input. When the latch enable goes
low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high
logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what
signals are present at the other inputs and the state of the strage elements.
Features
Input/Output are at high impedance state when power supply is off.
Built in input pull up circuit can make input pins be open, when not used.
TTL level input
Wide operating temperature range
Ta = –40 to + 85°C
Function Table
Inputs
G CK
HX
L
L
LL
H : High level
L : Low level
X : Immaterial
Z : High impedance
: Low to high transitions
D
X
L
H
X
Output Q
Z
H
L
No change

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HD74BC534A pdf
Switching Test Method (CL = 50 pF)
Item
Symbol
Propagation
CK Q tPLH
delay time
t PHL
Output enable time
t ZH
t ZL
Output disable time
t HZ
t LZ
Setup time
ts(H)
ts(L)
Hold time
th(H)
th(L)
Pulse width
tw(H)
tw(L)
Input capacitance
CIN
Output capacitance
CO
Ta = 25°C
VCC = 5.0 V
Min Max
3.0 8.0
3.0 8.0
3.0 9.0
3.0 9.0
3.0 8.0
3.0 8.0
2.0 —
2.0 —
2.0 —
2.0 —
6.0 —
6.0 —
3.0(Typ)
15.0(Typ)
HD74BC534A
Ta = –40 to 85°C
VCC = 5.0 V ±10%
Min Max
3.0 10.0
3.0 10.0
3.0 11.0
3.0 11.0
3.0 10.0
3.0 10.0
2.0 —
2.0 —
2.0 —
2.0 —
6.0 —
6.0 —
Unit Test Conditions
ns See under figure
ns
ns
ns
ns
ns
pF VIN = VCC or GND
pF VO = VCC or GND
Test Circuit
VCC
Input
Pulse Generator
Zout = 50
Input
Pulse Generator
Zout = 50
VCC
Output
G
1Q to 8Q
1D to 8D
CL =
50 pF
450
50 Scope
CK
Notes:
1. CL includes probe and jig capacitance.
2. OPEN: tPLH, tPHL, tZH, tHZ, th, ts, tw
7V: tZL, tLZ
OPEN
7V *2
5

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