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PDF HD74ALVCH162831 Data sheet ( Hoja de datos )
| Número de pieza | HD74ALVCH162831 | |
| Descripción | 1-bit 4-bit Address Register / Driver with 3-state Outputs | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HD74ALVCH162831
1-bit 4-bit Address Register / Driver with 3-state Outputs
ADE-205-195 (Z)
Preliminary
1st. Edition
March 1998
Description
This 1-bit to 4-bit address register / driver is designed for 2.3 V to 3.6 V VCC operation. The device is ideal
for use in applications in which a single address bus is driving four separate memory locations. The
HD74ALVCH162831 can be used as a buffer or a register, depending on the logic level of the select (SEL)
input. When SEL is logic high, the device is in the buffer mode. The outputs follow the inputs and are
controlled by the two output enable (OE) controls. Each OE controls two groups of nine outputs. When
SEL is logic low, the device is in the register mode. The register is an edge triggered D-type flip flop. On
the positive transition of the clock (CLK) input, data set up at the A inputs is stored in the internal registers.
OE controls operate the same as in buffer mode. When OE is logic low, the outputs are in a normal logic
state (high or low logic level). When OE is logic high, the outputs are in the high impedance state. To
ensure the high impedance state during power up or power down, OE should be tied to VCC through a
pullup registor; the minimum value of the registor is determined by the current sinking capability of the
driver. SEL and OE do not affect the internal operation of the flip flops. Old data can be retained or new
data can be entered while the outputs are in the high impedance state. Active bus hold circuitry is provided
to hold unused or floating data inputs at a valid logic level. All outputs, which are designed to sink up to
12 mA, include 26 Ω resistors to reduce overshoot and undershoot.
Features
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±12 mA (@VCC = 3.0 V)
• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors.
• All outputs have equivalent 26 Ω series resistors, so no external resistors are required.
1 page  
Logic Diagram
OE1 20
OE2 21
CLK 19
A1 8
SEL 22
CLK
DQ
HD74ALVCH162831
5 1Y1
4 2Y1
2 3Y1
1 4Y1
To eight other channels
5
5 Page 
HD74ALVCH162831
Waveforms – 3
Output
Control
tf
90 %
Vref
10 %
tZL
Waveform - A
Vref
tZH
Waveform - B
Vref
tr
10 %
90 %
Vref
tLZ
Vref1
tHZ
Vref2
VIH
GND
≈VOH1
VOL
VOH
≈VOL1
Notes:
TEST
VIH
Vref
Vref1
Vref2
VOH1
VOL1
Vcc=2.5±0.2V
VCC
Vcc=2.7V,
3.3±0.3V
2.7 V
1/2 VCC
1.5 V
VOL +0.15 V VOL +0.3 V
VOH–0.15 V VOH–0.3 V
VCC 3.0 V
GND
GND
1. All input pulses are supplied by generators having the following characteristics :
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.0 ns, tf ≤ 2.0 ns. (VCC = 2.5±0.2 V)
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. (VCC = 2.7 V, 3.3±0.3 V)
2. Waveform – A is for an output with internal conditions such that the output is low except
when disabled by the output control.
3. Waveform – B is for an output with internal conditions such that the output is high except
when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet HD74ALVCH162831.PDF ] | |
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