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PDF HD74ALVCH16269 Data sheet ( Hoja de datos )
| Número de pieza | HD74ALVCH16269 | |
| Descripción | 12-bit to 24-bit Registered Bus Transceivers with 3-state Outputs | |
| Fabricantes | Hitachi Semiconductor | |
| Logotipo |  |
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HD74ALVCH16269
12-bit to 24-bit Registered Bus Transceivers
with 3-state Outputs
ADE-205-136 (Z)
Preliminary 1st. Edition
May 1996
Description
The HD74ALVCH16269 is used in applications where two separate ports must be multiplexed onto, or
demultiplexed from, a single port. The device is particularly suitable as an interface between
synchronous DRAMs and high speed microprocessors. Data is stored in the internal B port registers on
the low to high transition of the clock (CLK) input when the appropriate clock enable (CLKENA)
inputs are low. Proper control of these inputs allows two sequential 12-bit words to be presented as a
24-bit word on the B port. For data transfer in the B to A direction, a single storage register is
provided. The select (SEL) line selects 1B or 2B data for the A outputs. The register on the A output
permits the fastest possible data transfer, thus extending the period that the data is valid on the bus.
The control terminals are registered so that all transactions are synchronous with CLK. Data flow is
controlled by the active low output enables (OEA, OEB1, OEB2). Active bus hold circuitry is
provided to hold unused or floating data inputs at a valid logic level.
Features
• VCC = 2.3 V to 3.6 V
• Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C)
• Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C)
• High output current ±24 mA (@VCC = 3.0 V)
• Bus hold on data inputs eliminates the need for external pullup / pulldown resistors
1 page  
Logic Diagram
HD74ALVCH16269
29
CLK
OEB1 2
OEB2
CLKENA1
CLKENA2
SEL
OEA
56
30
55
28
1
1D
C1
8
A1
C1
1D
C1
1D
C1
1D
G1
1
1
CE
C1
1D
CE
C1
1D
1 of 12 Channels
C1
1D
23
1B1
6
2B1
5 Page 
HD74ALVCH16269
• Waveforms – 3
tf
Output
Control
90 %
Vref
10 %
tZL
Waveform - A
Vref
tZH
Waveform - B
Vref
tr
10 %
90 %
Vref
tLZ
tHZ
VOL + 0.3 V
VOH – 0.3 V
VIH
GND
≈VOH1
VOL
VOH
≈VOL1
TEST
VIH
Vref
VOH1
VOL1
Vcc=2.5±0.2V
2.3 V
1.2 V
2.3 V
GND
Vcc=2.7V,
3.3±0.3V
2.7 V
1.5 V
3.0 V
GND
Notes: 1. All input pulses are supplied by generators having the following characteristics:
PRR ≤ 10 MHz, Zo = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
2. Waveform – A is for an output with internal conditions such that the output is low
except when disabled by the output control.
3. Waveform – B is for an output with internal conditions such that the output is high
except when disabled by the output control.
4. The output are measured one at a time with one transition per measurement.
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet HD74ALVCH16269.PDF ] | |
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