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HD6475328CGのメーカーはHitachi Semiconductorです、この部品の機能は「Manual Gives a Hardware Description」です。 |
部品番号 | HD6475328CG |
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部品説明 | Manual Gives a Hardware Description | ||
メーカ | Hitachi Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとHD6475328CGダウンロード(pdfファイル)リンクがあります。 Total 30 pages
H8/532 Hardware Manual
1 Page Contents
Section 1 Overview
1.1 Features ··································································································································1
1.2 Block Diagram ·······················································································································4
1.3 Pin Arrangements and Functions ···························································································5
1.3.1 Pin Arrangement ·········································································································5
1.3.2 Pin Functions ··············································································································8
Section 2 MCU Operating Modes and Address Space
2.1 Overview ······························································································································23
2.2 Mode Descriptions ···············································································································24
2.3 Address Space Map ··············································································································25
2.3.1 Page Segmentation ····································································································25
2.3.2 Page 0 Address Allocations ······················································································27
2.4 Mode Control Register (MDCR) ·························································································29
Section 3 CPU
3.1 Overview ······························································································································31
3.1.1 Features ·····················································································································31
3.1.2 Address Space ···········································································································32
3.1.3 Register Configuration ······························································································33
3.2 CPU Register Descriptions ··································································································34
3.2.1 General Registers ······································································································34
3.2.2 Control Registers ······································································································35
3.2.3 Initial Register Values ·······························································································40
3.3 Data Formats ························································································································41
3.3.1 Data Formats in General Registers ···········································································41
3.3.2 Data Formats in Memory ··························································································42
3.4 Instructions ···························································································································44
3.4.1 Basic Instruction Formats ·························································································44
3.4.2 Addressing Modes ····································································································45
3.4.3 Effective Address Calculation ···················································································47
3.5 Instruction Set ······················································································································50
3.5.1 Overview ···················································································································50
3.5.2 Data Transfer Instructions ·························································································52
3.5.3 Arithmetic Instructions ·····························································································53
3.5.4 Logic Operations ·······································································································54
3.5.5 Shift Operations ········································································································55
3.5.6 Bit Manipulations ······································································································56
3.5.7 Branching Instructions ······························································································57
3Pages 6.3.1 Data Transfer Cycle ································································································118
6.3.2 DTC Vector Table ···································································································120
6.3.3 Location of Register Information in Memory ·························································122
6.3.4 Length of Data Transfer Cycle ················································································122
6.4 Procedure for Using the DTC ····························································································124
6.5 Example ·····························································································································125
Section 7 Wait-State Controller
7.1 Overview ····························································································································127
7.1.1 Features ···················································································································127
7.1.2 Block Diagram ········································································································128
7.1.3 Register Configuration ····························································································128
7.2 Wait-State Control Register ·······························································································129
7.3 Operation in Each Wait Mode ····························································································130
7.3.1 Programmable Wait Mode ······················································································130
7.3.2 Pin Wait Mode ········································································································131
7.3.3 Pin Auto-Wait Mode ·······························································································133
Section 8 Clock Pulse Generator
8.1 Overview ····························································································································135
8.1.1 Block Diagram ········································································································135
8.2 Oscillator Circuit ················································································································135
8.3 System Clock Divider ········································································································138
Section 9 I/O Ports
9.1 Overview ····························································································································139
9.2 Port 1 ··································································································································142
9.2.1 Overview ·················································································································142
9.2.2 Port 1 Registers ·······································································································142
9.2.3 Pin Functions in Each Mode ···················································································145
9.3 Port 2 ··································································································································148
9.3.1 Overview ·················································································································148
9.3.2 Port 2 Registers ·······································································································149
9.3.3 Pin Functions in Each Mode ···················································································150
9.4 Port 3 ··································································································································151
9.4.1 Overview ·················································································································151
9.4.2 Port 3 Registers ·······································································································152
9.4.3 Pin Functions in Each Mode ···················································································153
9.5 Port 4 ··································································································································154
9.5.1 Overview ·················································································································154
9.5.2 Port 4 Registers ·······································································································155
6 Page | |||
ページ | 合計 : 30 ページ | ||
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PDF ダウンロード | [ HD6475328CG データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
HD6475328CG | Manual Gives a Hardware Description | Hitachi Semiconductor |
HD6475328CG | Manual Gives a Hardware Description | Hitachi Semiconductor |
HD6475328CP | Manual Gives a Hardware Description | Hitachi Semiconductor |
HD6475328CP | Manual Gives a Hardware Description | Hitachi Semiconductor |