PDF HD6437020VXI Data sheet ( Hoja de datos )

Número de pieza	HD6437020VXI
Descripción	SuperH RISC engine
Fabricantes	Hitachi Semiconductor
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No Preview Available ! SuperH™ RISC engine SH7020 and SH7021 HD6437020, HD6477021, HD6437021, HD6417021 Hardware Manual ADE-602-074B Rev. 3.0 11/25/99 Hitachi, Ltd. 1 page Organization of This Manual Table 1 describes how this manual is organized. Figure 1 shows the relationships between the Sections within this manual. Table 1 Manual Organization Category Overview Section Title 1. Overview CPU 2. CPU Operating Modes Internal Modules Clock Buses Timers 3. Operating Modes 4. Exception Processing 5. Interrupt Controller 6. User Break Controller 7. Clock Pulse Generator 8. Bus State Controller 9. Direct Memory Access Controller 10. 16-Bit Integrated- Timer Pulse Unit Data Processing 11. Programmable Timing Pattern Controller 12. Watchdog Timer 13. Serial Communica- tion Interface Abbrevi- ation — CPU — — INTC UBC CPG BSC DMAC ITU TPC WDT SCI Contents Features, internal block diagram, pin layout, pin functions Register configuration, data structure. instruction features, instruction types, instruction lists MCU mode, PROM mode Resets, address errors, interrupts, trap instructions, illegal instructions NMI interrupts, user break interrupts, IRQ interrupts, on-chip module interrupts Break address and break bus cycles selection Crystal pulse generator, duty correction circuit Division of memory space, DRAM interface, refresh, wait state control, parity control Auto request, external request, on-chip peripheral module request, cycle steal mode, burst mode Waveform output mode, input capture function, counter clear function, buffer operation, PWM mode, complementary PWM mode, reset synchronized mode, synchronized operation, phase counting mode, compare match output mode Compare match output triggers, non-overlap operation Watchdog timer mode, interval timer mode Asynchronous mode, clock synchronous mode, multiprocessor communication function 5 Page 5.3.2 Interrupt Control Register (ICR) .......................................................................... 69 5.4 Interrupt Operation ............................................................................................................ 70 5.4.1 Interrupt Sequence................................................................................................ 70 5.4.2 Stack after Interrupt Exception Processing .......................................................... 72 5.5 Interrupt Response Time.................................................................................................... 73 5.5 Usage Notes ....................................................................................................................... 74 Section 6 User Break Controller (UBC)........................................................................ 6.1 Overview............................................................................................................................ 6.1.1 Features ................................................................................................................ 6.1.2 Block Diagram...................................................................................................... 6.1.3 Register Configuration ......................................................................................... 6.2 Register Descriptions......................................................................................................... 6.2.1 Break Address Registers (BAR) .......................................................................... 6.2.2 Break Address Mask Register (BAMR)............................................................... 6.2.3 Break Bus Cycle Register (BBR) ......................................................................... 6.3 Operation ........................................................................................................................... 6.3.1 Flow of the User Break Operation........................................................................ 6.3.2 Break on Instruction Fetch Cycles to On-Chip Memory...................................... 6.3.3 Program Counter (PC) Value Saved in User Break Interrupt Exception Processing............................................................................................................. 6.4 Setting User Break Conditions .......................................................................................... 6.5 Notes.................................................................................................................................. 6.5.1 On-Chip Memory Instruction Fetch ..................................................................... 6.5.2 Instruction Fetch at Branches ............................................................................... 6.5.3 Instruction Fetch Break ........................................................................................ 75 75 75 75 76 77 77 78 79 81 81 84 84 84 86 86 86 87 Section 7 Clock Pulse Generator (CPG) ....................................................................... 7.1 Overview............................................................................................................................ 7.2 Clock Source...................................................................................................................... 7.2.1 Connecting a Crystal Resonator ........................................................................... 7.2.2 External Clock Input ............................................................................................ 7.3 Usage Notes ....................................................................................................................... 89 89 89 89 90 91 Section 8 Bus State Controller (BSC)............................................................................ 8.1 Overview............................................................................................................................ 8.1.1 Features ................................................................................................................ 8.1.2 Block Diagram...................................................................................................... 8.1.3 Pin Configuration ................................................................................................. 8.1.4 Register Configuration ......................................................................................... 8.1.5 Overview of Areas................................................................................................ 8.2 Register Descriptions......................................................................................................... 8.2.1 Bus Control Register (BCR) ................................................................................ 93 93 93 93 95 95 96 97 97 11 Page

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