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PDF MB1519 Data sheet ( Hoja de datos )
| Número de pieza | MB1519 | |
| Descripción | DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER | |
| Fabricantes | Fujitsu | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MB1519 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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DS04–21314–1E
MB1519 ASSP
DATA SHEET
DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER
DUAL SERIAL INPUT PLL FREQUENCY SYNTHESIZER
WITH 600MHz PRESCALER
The Fujitsu MB1519 is a 600MHz dual serial input PLL (Phase Locked) frequency synthesizer
designed for cellular telephone and cordless telephone applications.
The MB1519 has two PLL circuits on a single chip: one for transmit and the other for reception.
Separate power supply pins are provided for the transmit and reception PLL circuits. Transmit
PLL contains a low sensitivity charge pump for ease of modulation and reception PLL contains a
high sensitivity charge pump for faster lock up time.
600 MHz dual modulus prescalers are on chip and enables a pulse swallow function.
It operates supply voltage of 3.0V typ. and dissipates 11mA typ. of current realized through the
use of Fujitsu’s unique U-ESBIC Bi-CMOS technology.
• High operating frequency: fin = 600MHz
• Low power supply voltage: VCC = 2.7 to 5.5V
• Low power supply current: ICC = 11mA typ, @3V.
• Wide operating temperature: TA = –40 to 85°C
• Two charge pumps
Low sensitivity charge pump for transmit
High sensitivity charge pump for reception
• Plastic 20-pin dual in line package (Suffix: -P)
Plastic 20-pin flat package (Suffix: -PF)
ABSOLUTE MAXIMUM RATINGS (see NOTE)
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
VP
–0.5 to 7.0
VCC to 10.0
V
Output Voltage
VOUT
–0.5 to VCC +0.5
V
Output Current
IOUT
±10
mA
Storage Temperature
TSTG
–55 to +125
°C
PLASTIC PACKAGE
DIP-20P-M02
PLASTIC PACKAGE
FPT-20P-M01
PIN ASSIGNMENT
GND
OSCIN
OSCOUT
fin1
VCC1
fr
LD1
VP1
DO1
BS1
1 20
2 19
3 18
4 17
5 TOP 16
6 VIEW 15
7 14
8 13
9 12
10 11
Data
Data
LE
fin2
VCC2
fp
LD2
VP2
DO2
BS2
NOTE:
Permanent device damage may occur if the above Absolute Maximum Ratings
are exceeded. Functional operation should be restricted to the conditions as
detailed in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However,
it is advised that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages
to this high impedance circuit.
©Copyright 1994 by FUJITSU LIMIED
1
1 page  
PIN DESCRIPTIONS (Continued)
MB1519
Pin No. Pin Name
16 VCC2
I/O
–
17 fin2
18 LE
I
I
19 Data
I
Descriptions
Power supply voltage input pin for reception section, programmable reference divider, shift register,
and crystal oscillator.
When power is OFF, latched data of reception section and reference counter is cancelled.
Prescaler input pin of reception section.
The connection with VCO should be AC conneciton.
Load enable input pin. This pin involves a schmitt trigger circuit.
When this pin is high, the data stored in the shift register is transferred into the latch depending on a
control data.
At this moment, charge pump output signal is output from BS pin since internal analog swith becomes
ON.
Serial data input pin of 23-bit shift register. This pin involves a schmitt trigger circuit.
The stored data in the shift register is transferred to either transmit section or reception section
depending upon a control data.
Control bit data
H
L
The destination of data
Latch of transmit section
Latch of reception section
20 Clock I Clock input pin of 23-bit shift register. This pin involves a schmitt trigger circuit.
On rising edge of the clock shifts one bit of data into the shift register.
FUNCTIONAL DESCRIPTIONS
The divide ratio can be calculated using the following equation:
fVCO = {(M x N) + A} x fOSC ÷ R (A < N)
fVCO: Output frequency of external voltage controlled ocillator (VCO)
M: Preset divide ratio of dual modulus prescaler (64)
N: Preset divide ratio of binary 11-bit programmable counter (16 to 2047)
A: Preset divide ratio of binary 7-bit swallow counter (0≤ A ≤ 127)
fOSC: Reference oscillator frequency
R: Preset divide ratio of reference counter (512 or 1024)
5
5 Page 
MB1519
TEST CIRCUIT (PRESCALER INPUT SENSITIVITY TEST)
VP1
VCC1
X’tal
0.1µF
0.1µF
1000pF
P.G
GND
8 5 4 3 21
50Ω
MB1519
13 15 16 17 18 19 20
P.G
1000pF
50Ω
VP2
VCC2
fp
Oscilloscope
0.1µF
0.1µF
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet MB1519.PDF ] | |
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