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PDF W78E052D Data sheet ( 特性 )

部品番号 W78E052D
部品説明 8-BIT MICROCONTROLLER
メーカ Nuvoton
ロゴ Nuvoton ロゴ 

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W78E052D Datasheet, W78E052D PDF,ピン配置, 機能
W78E054D/W78E052D Data Sheet
1 GENERAL DESCRIPTION
The W78E054D/W78E052D series is an 8-bit microcontroller which can accommodate a wider fre-
quency range with low power consumption. The instruction set for the W78E054D/W78E052D series is
fully compatible with the standard 8052.
The W78E054D/W78E052D series contains 16K/8K bytes Flash EPROM programmable by hardware
writer; a 256 bytes RAM; four 8-bit bi-directional (P0, P1, P2, P3) and bit-addressable I/O ports; an ad-
ditional 4-bit I/O port P4; three 16-bit timer/counters; a hardware watchdog timer and a serial port. The-
se peripherals are supported by 8 sources 4-level interrupt capability. To facilitate programming and
verification, the Flash EPROM inside the W78E054D/W78E052D series allows the program memory to
be programmed and read electronically. Once the code is confirmed, the user can protect the code for
security.
The W78E054D/W78E052D series microcontroller has two power reduction modes, idle mode and
power-down mode, both of which are software selectable. The idle mode turns off the processor clock
but allows for continued peripheral operation. The power-down mode stops the crystal oscillator for
minimum power consumption. The external clock can be stopped at any time and in any state without
affecting the processor. The W78E054D/W78E052D series contains In-System Programmable (ISP)
2KB LDROM for loader program, operating voltage from 3.3V to 5.5V.
Note: If the applied VDD is not stable, especially with long transition time of power on/off, it’s
recommended to apply an external RESET IC to the RST pin for improving the stability of sys-
tem.
-4-
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W78E052D pdf, ピン配列
W78E054D/W78E052D Data Sheet
3 PARTS INFORMATION LIST
PART NO.
W78E054DDG
W78E054DPG
W78E054DFG
W78E054DTG
W78E054DLG
W78E052DDG
W78E052DPG
W78E052DFG
W78E052DTG
W78E052DLG
RAM
LDROM
SIZE
APROM
SIZE
PACKAGE
2K Bytes
0
14K Bytes
16K Bytes
DIP-40 Pin
2K Bytes
0
14K Bytes
16K Bytes
PLCC-44 Pin
2K Bytes
0
14K Bytes
16K Bytes
PQFP-44 Pin
256
Bytes
2K Bytes
0
2K Bytes
0
14K Bytes
16K Bytes
14K Bytes
16K Bytes
TQFP-44 Pin
LQFP-48 Pin
DIP-40 Pin
PLCC-44 Pin
2K Bytes 8K Bytes PQFP-44 Pin
TQFP-44 Pin
LQFP-48 Pin
Table 31: Lad Free (RoHS) Parts information list
Temperature
grade
-40oC~85oC
-40oC~85oC
-40oC~85oC
-40oC~85oC
-40oC~85oC
-40oC~85oC
-40oC~85oC
-40oC~85oC
-40oC~85oC
-40oC~85oC
-6-


3Pages


W78E052D 電子部品, 半導体
W78E054D/W78E052D Data Sheet
5 PIN DESCRIPTIONS
SYMBOL
EA
TYPE DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM address
I and data will not be present on the bus if EA pin is high and the program coun-
ter is within internal ROM area. Otherwise they will be present on the bus.
PSEN
ALE
RST
XTAL1
XTAL2
VSS
VDD
P0.0P0.7
P1.0P1.7
P2.0P2.7
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the
O H Port 0 address/data bus during fetch and MOVC operations. When internal ROM
access is performed, no PSEN strobe signal outputs from this pin.
OH
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that sepa-
rates the address from the data on Port 0.
IL
RESET: A high on this pin for two machine cycles while the oscillator is running
resets the device.
I
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an ex-
ternal clock.
O CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
I GROUND: Ground potential
I POWER SUPPLY: Supply voltage for operation.
I/O D
PORT 0: Port 0 is an open-drain bi-directional I/O port. This port also provides a
multiplexed low order address/data bus during accesses to external memory.
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have
alternate functions which are described below:
I/O H T2 (P1.0): Timer/Counter 2 external count input
T2EX (P1.1): Timer/Counter 2 Reload/Capture control
I/O H
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
Publication Release Date: Aug 31, 2012
- 9 - Revision A12

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