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DTC34LF86LのメーカーはDOESTEKです、この部品の機能は「+3.3V LVDS 24Bit Flat Panel Display (FPD) Receiver」です。 |
部品番号 | DTC34LF86L |
| |
部品説明 | +3.3V LVDS 24Bit Flat Panel Display (FPD) Receiver | ||
メーカ | DOESTEK | ||
ロゴ | |||
このページの下部にプレビューとDTC34LF86Lダウンロード(pdfファイル)リンクがあります。 Total 7 pages
DTC34LF8 6L/DTC34LR86L
LVDS Product
DTC34LF86L/DTC34LR86L (Rev. 2.2)
REVISED APR. 2009
+3.3V LVDS 24Bit Flat Panel Display (FPD) Receiver - 85MHz
General Description
The D TC34LF86L/LR86L rec eivers co nvert the L VDS
(Low Voltage Differential Signaling) data streams back
into 28 bit s of CMOS/ TTL dat a with falling edge
(DTC34LF86L) or risin g edge (DTC34LR86L) clock for
convenient int erface with a variet y of L CD p anel
controllers.
A phase-locked transmit clock is transmitte d in p arallel
with the data streams ove r a fif th L VDS link. A
transmitter (DTC34LM85L) w ill inter-o perate w ith a
Falling/Rising edg e rec eiver (DT C34LF86L/LR86L)
without any translation logic.
Using a 8 5 MHz clock, the dat a throu ghputs is 297.5
Mbytes/sec. This chip set is an ide al mean s to solve
EMI and ca ble size problems associat ed with wide,
high speed TTL interfaces.
Features
▓ Wide frequency range : 20 to 85 MHz shift
clock support
▓ Narrow bus (10 lines) reduces cable size
▓ Sing le 3.3V supply
▓ Po wer-Down Mode
▓ Single pixel per clock XGA (1024x768) ready
▓ Supports VGA, SVGA, XGA and SXGA
▓ Up to 297.5 Megabytes/sec bandwidth
▓ Up to 2.38 Gbps throughput
▓ 300mV swing LVDS devices for low EMI
▓ PLL requires no external components
▓ Low profile 56-lead TSSOP package (PB Free)
▓ Comp atible with TIA/EIA-644 LVDS standard
▓ Compatible with the National DS90C386,
T hine THC63LVDF84A
Block Diagram
DTC34LF86L/DTC34LR86L
CMOS/TTL OUTPUTS
8
RED
LVDS DATA
( 140 TO 595Mbit/s
On Each LVDS
Channel )
8
GRN
8
BLU
HSYNC
VSYNC
DE(Data Enable)
CNTL
RCLK+/-
(20MHz ~ 85MHz)
PLL CLKOUT
(20MHz ~ 85MHz)
/PDN(Power Down)
-1-
DOESTEK Co., Ltd.
http://www.Datasheet4U.com
1 Page DTC34LF8 6L/DTC34LR86L
Receiver Switching Characteristics
Vcc=3.0 ~ 3.6V @ Ta=-10 ~ +70°C, T=1/f
Symbol Para
meter
Min Typ Max Units
tRCP CLKOUT Period
11.76
T
50 nS
tRCH CLKOUT High Time
4.5 5.0 7.0 nS
tRCL CLKOUT Low Time
tRCD RCLK+/- to CLKOUT Delay
4.0 5.0 6.5 nS
7.0 nS
tRS TTL Data Setup to CLKOUT
3.5
nS
tRH TTL Data Hold from CLKOUT
tTLH TTL Low to High Transition Time
3.5
3
nS
nS
tTHL TTL High to Low Transition Time
3 nS
tRDP5
tRDP6
Receiver Input Data Position 0 (85MHz)
Receiver Input Data Position 1 (85MHz)
-0.4
T/7-0.4
0 0.4 nS
T/7
T/7+0.4
nS
tRDP0
Receiver Input Data Position 2 (85MHz)
2T/7-0.4
2T/7
2T/7+0.4
nS
tRDP1
tRDP2
Receiver Input Data Position 3 (85MHz)
Receiver Input Data Position 4 (85MHz)
3T/7-0.4
4T/7-0.4
3T/7
4T/7
3T/7+0.4
4T/7+0.4
nS
nS
tRDP3
Receiver Input Data Position 5 (85MHz)
5T/7-0.4
5T/7
5T/7+0.4
nS
tRDP4
tRPLLS
Receiver Input Data Position 6 (85MHz)
Receiver Phase Lock Loop Set
PIN OUT
6T/7-0.4
6T/7
PACKAGE
6T/7+0.4
10
nS
mS
RX22 1
RX23 2
RX24 3
GND 4
RX25 5
RX26 6
RX27 7
LVDS GND 8
RL0- 9
RL0+ 10
RL1- 11
RL1+ 12
LVDS VCC 13
LVDS GND 14
RL2- 15
RL2+ 16
RCLK- 17
RCLK+ 18
RL3- 19
RL3+ 20
LVDS GND 21
PLL GND 22
PLL VCC 23
PLL GND 24
/PDN 25
CLKOUT 26
RX0 27
GND 28
56 VCC
55 RX21
54 RX20
53 RX19
52 GND
51 RX18
50 RX17
49 RX16
48 VCC
47 RX15
46 RX14
45 RX13
44 GND
43 RX12
42 RX11
41 RX10
40 VCC
39 RX9
38 RX8
37 RX7
36 GND
35 RX6
34 RX5
33 RX4
32 RX3
31 VCC
30 RX2
29 RX1
56 Lead Molded Thin Shrink Small Outline Package, JEDEC
U nit : millimeters
14.0 ± 0.1
56
29
8.1 ± 0.1
4.05
1
0.5 TYP
0.2 TYP
6.1 ± 0.1
28 (1.0)
1.2MAX
0.10 ± 0.05 TYP
- 3 - DOESTEK Co., Ltd.
3Pages DTC34LF8 6L/DTC34LR86L
FIGURE 6. LVDS Inputs Mapped Parallel TTL Data Outputs – DTC34LF86L/DTC34LR86L
RCLK
Previous Cycle
(Differential)
RL3
(Single Ended)
RL2
(Single Ended)
RL1
(Single Ended)
RX5-1
RX27-1
RX23
RX20-1 RX19-1
RX26
RX9-1
RX8-1
RX18
RL0
(Single Ended)
RX1-1
RX0-1
RX7
RX17
RX25
RX15
RX6
Next Cycle
RX16
RX11
RX10
RX24
RX22
RX21
RX14
RX13
RX12
RX4 RX3 RX2
RX5
RX20
RX9
RX1
RX27
RX19
RX8
RX0
FIGURE 7. Setup/Hold and High/Low Times
CLKOUT
2.0V
tRCH
2.0V
0.8V
tRCL
0.8V
RX0 ~ RX27
2.0V
0.8V
tRS
Setup
tRH
Hold 2.0V
0.8V
Note : 1) CLKOUT: for DTC34LF86L, denoted as solid line(dotted line is for DTC34LR86L),
FIGURE 8. RCLK to CLKOUT Delay
RCLK +/-
CLKOUT 2.0V
Vdiff = 0V
tRCD
2.0V
1.5V
tRCP
Note : 1) Vdiff = (RL+) - (RL-), .... (RCLK+) - (RCLK-)
-6-
DOESTEK Co., Ltd.
6 Page | |||
ページ | 合計 : 7 ページ | ||
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部品番号 | 部品説明 | メーカ |
DTC34LF86L | +3.3V LVDS 24Bit Flat Panel Display (FPD) Receiver | DOESTEK |