PDF HD4-6409-9 Data sheet ( Hoja de datos )

Número de pieza	HD4-6409-9
Descripción	CMOS Manchester Encoder-Decoder
Fabricantes	Intersil Corporation
Logotipo
Hay una vista previa y un enlace de descarga de HD4-6409-9 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas
No Preview Available ! HD-6409 March 1997 CMOS Manchester Encoder-Decoder Features • Converter or Repeater Mode • Independent Manchester Encoder and Decoder Operation • Static to One Megabit/sec Data Rate Guaranteed • Low Bit Error Rate • Digital PLL Clock Recovery • On Chip Oscillator • Low Operating Power: 50mW Typical at +5V • Available in 20 Lead Dual-In-Line and 20 Pad LCC Package Ordering Information PACKAGE PDIP SOIC CERDIP DESC CLCC DESC TEMPERATURE RANGE -40oC to +85oC -40oC to +85oC -40oC to +85oC -55oC to 125oC -40oC to +85oC -55oC to 125oC 1 MEGABIT/SEC HD3-6409-9 HD9P6409-9 HD1-6409-9 5962-9088801MRA HD4-6409-9 5962-9088801M2A PKG. NO. E20.3 M20.3 F20.3 F20.3 J20.A J20.A Description The HD-6409 Manchester Encoder-Decoder (MED) is a high speed, low power device manufactured using self-aligned sil- icon gate technology. The device is intended for use in serial data communication, and can be operated in either of two modes. In the converter mode, the MED converts Non return-to-Zero code (NRZ) into Manchester code and decodes Manchester code into Nonreturn-to-Zero code. For serial data communication, Manchester code does not have some of the deﬁciencies inherent in Nonreturn-to-Zero code. For instance, use of the MED on a serial line eliminates DC components, provides clock recovery, and gives a relatively high degree of noise immunity. Because the MED converts the most commonly used code (NRZ) to Manchester code, the advantages of using Manchester code are easily realized in a serial data link. In the Repeater mode, the MED accepts Manchester code input and reconstructs it with a recovered clock. This mini- mizes the effects of noise on a serial data link. A digital phase lock loop generates the recovered clock. A maximum data rate of 1MHz requires only 50mW of power. Manchester code is used in magnetic tape recording and in ﬁber optic communication, and generally is used where data accuracy is imperative. Because it frames blocks of data, the HD-6409 easily interfaces to protocol controllers. Pinouts HD-6409 (CERDIP, PDIP, SOIC) TOP VIEW HD-6409 (CLCC) TOP VIEW BZI 1 BOI 2 UDI 3 SD/CDS 4 SDO 5 SRST 6 NVM 7 DCLK 8 RST 9 GND 10 20 VCC 19 BOO 18 BZO 17 SS 16 ECLK 15 CTS 14 MS 13 OX 12 IX 11 CO 3 2 1 20 19 SD/CDS 4 18 BZO SDO 5 17 SS SRST 6 16 ECLK NVM 7 15 CTS DCLK 8 14 MS 9 10 11 12 13 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 \| Copyright © Intersil Corporation 1999 5-1 File Number 2951.1 1 page HD-6409 There is a three bit delay between UDI, BOl, or BZI input and the decoded NRZ data transmitted out of SDO. Control of the decoder outputs is provided by the RST pin. When RST is low, SDO, DCLK and NVM are forced low. When RST is high, SDO is transmitted out synchronously with the recovered clock DCLK. The NVM output remains low after a low to high transition on RST until a valid sync pattern is received. The decoded data at SDO is in NRZ format. DCLK is pro- vided so that the decoded bits can be shifted into an external register on every high to low transition of this clock. Three bit periods after an invalid Manchester bit is received on UDI, or BOl, NVM goes low synchronously with the questionable data output on SDO. FURTHER, THE DECODER DOES NOT REESTABLISH PROPER DATA DECODING UNTIL ANOTHER SYNC PATTERN IS RECOGNIZED. DCLK UDI SDO COMMAND SYNC 1 00 10 101 0101 0 RST NVM FIGURE 2. DECODER OPERATION Repeater Operation Manchester Il data can be presented to the repeater in either of two ways. The inputs Bipolar One In and Bipolar Zero In will accept data from differential inputs such as a comparator or sensed transformer coupled bus. The input Unipolar Data In accepts only noninverted Manchester II coded data. The decoder requires a single clock with a frequency 16X or 32X the desired data rate. This clock is selected to 16X with Speed Select low and 32X with Speed Select high. For long data links the 32X mode should be used as this permits a wider timing jitter margin. The inputs UDl, or BOl, BZl are delayed approximately 1/2 bit period and repeated as outputs BOO and BZO. The 2X ECLK is transmitted out of the repeater synchronously with BOO and BZO. A low on CTS enables ECLK, BOO, and BZO. In contrast to the converter mode, a transition on CTS does not initiate a synchronization sequence of eight 0’s and a command sync. The repeater mode does recognize a command or data sync pulse. SD/CDS is an output which reﬂects the state of the most recent sync pulse received, with high indicating a com- mand sync and low indicating a data sync. When RST is low, the outputs SDO, DCLK, and NVM are low, and SRST is set low. SRST remains low after RST goes high and is not reset until a sync pulse and two valid manchester bits are received with the reset bit low. The reset bit is the ﬁrst data bit after the sync pulse. With RST high, NRZ Data is transmitted out of Serial Data Out synchro- nously with the 1X DCLK. INPUT COUNT 1 2 34 56 7 ECLK SYNC PULSE UDI BZO BOO RST SRST FIGURE 3. REPEATER OPERATION 5-5 5 Page Timing Waveforms (Continued) HD-6409 CTS BZO BOO ECLK ECLK SD/CDS BZO BOO tCE1 tCE2 tCE3 FIGURE 11. ENCODER TIMING tCE4 tCE5 FIGURE 12. ENCODER TIMING CTS ECLK BZO BOO tCE6 tCE7 FIGURE 13. ENCODER TIMING DCLK UDI SDO MANCHESTER MANCHESTER MANCHESTER MANCHESTER LOGIC-1 LOGIC-0 LOGIC-0 LOGIC-1 tCD1 tCD2 tCD5 NVM tCD2 NRZ LOGIC-1 NOTE: Manchester Data-In is not synchronous with Decoder Clock. Decoder Clock is synchronous with decoded NRZ out of SDO. FIGURE 14. DECODER TIMING RST DCLK, SDO, NVM 50% tCD3 50% FIGURE 15. DECODER TIMING RST 50% DCLK tCD4 FIGURE 16. DECODER TIMING 5-11 11 Page

Páginas	Total 12 Páginas
PDF Descargar	[ Datasheet HD4-6409-9.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
HD4-6409-9	CMOS Manchester Encoder-Decoder	Intersil Corporation

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar