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PDF CY7C63723C Data sheet ( Hoja de datos )
| Número de pieza | CY7C63723C | |
| Descripción | USB Combination Low-Speed USB and PS/2 Peripheral Controller | |
| Fabricantes | Cypress Semiconductor | |
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CY7C63722C
CY7C63723C
CY7C63743C
enCoRe™ USB Combination Low-Speed
USB and PS/2 Peripheral Controller
1.0 Features
• enCoRe™ USB - enhanced Component Reduction
— Internal oscillator eliminates the need for anexternal
crystal or resonator
— Interface can auto-configure to operate as PS/2 or
USB without the need for external components to
switch between modes (no General Purpose I/O
[GPIO] pins needed to manage dual mode capability)
— Internal 3.3V regulator for USB pull-up resistor
— Configurable GPIO for real-world interface without
external components
• Flexible, cost-effective solution for applications that
combine PS/2 and low-speed USB, such as mice,game-
pads, joysticks, and many others.
• USB Specification Compliance
— Conforms to USB Specification, Version 2.0
— Conforms to USB HID Specification, Version 1.1
— Supports one low-speed USB device address and
three data endpoints
— Integrated USB transceiver
— 3.3V regulated output for USB pull-up resistor
• 8-bit RISC microcontroller
— Harvard architecture
— 6-MHz external ceramic resonator or internal clock
mode
— 12-MHz internal CPU clock
— Internal memory
— 256 bytes of RAM
— 8 Kbytes of EPROM
— Interface can auto-configure to operate as PS/2 or
USB
— No external components for switching between PS/2
and USB modes
— No GPIO pins needed to manage dual mode
capability
• I/O ports
— Up to 16 versatile GPIO pins, individually
configurable
— High current drive on any GPIO pin: 50 mA/pin
current sink
— Each GPIO pin supports high-impedance inputs,
internal pull-ups, open drain outputs or traditional
CMOS outputs
— Maskable interrupts on all I/O pins
• SPI serial communication block
— Master or slave operation
— 2 Mbit/s transfers
• Four 8-bit Input Capture registers
— Two registers each for two input pins
— Capture timer setting with five prescaler settings
— Separate registers for rising and falling edge capture
— Simplifies interface to RF inputs for wireless
applications
• Internal low-power wake-up timer during suspend
mode
— Periodic wake-up with no external components
• Optional 6-MHz internal oscillator mode
— Allows fast start-up from suspend mode
• Watchdog Reset (WDR)
• Low-voltage Reset at 3.75V
• Internal brown-out reset for suspend mode
• Improved output drivers to reduce EMI
• Operating voltage from 4.0V to 5.5VDC
• Operating temperature from 0°C to 70°C
• CY7C63723C available in 18-pin SOIC, 18-pin PDIP
• CY7C63743C available in 24-pin SOIC, 24-pin PDIP,
24-pin QSOP
• CY7C63722C available in DIE form
• Industry standard programmer support
Cypress Semiconductor Corporation •
Document #: 38-08022 Rev. *C
198 Champion Court •
San Jose • CA 95 134 • 408-943-2600
Revised February 25, 2006
http://www.Datasheet4U.com
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FOR CY7C63722C
FOR
CY7C63723C
CY7C63743C
• DSPINIT: EQU 30h
• MOV A,DSPINIT
6.6.2 Direct
“Direct” add ress mode is use d wh en the dat a o perand i s a
variable stored in SRAM. In that case, the one byte address of
the variab le is enco ded in the instruction. As an e xample,
consider an in struction tha t l oads A with the con tents of
memory address location 0x10h:
• MOV A, [10h]
In no rmal usa ge, varia ble name s are a ssigned to variable
addresses using “EQU” statements to improve the readability
of the a ssembler source code. As an example, the following
code is equivalent to the example shown above.
• buttons: EQU 10h
• MOV A, [buttons]
6.6.3 Indexed
“Indexed” addre ss mod e allo ws th e fi rmware to manipulate
arrays of dat a stored i n SRAM. T he ad dress of th e dat a
operand is the sum of a constant encoded in the instruction
and the co ntents of th e “X” regi ster. In no rmal usa ge, the
constant will be the “base” address of an array of data and the
X register will contain an index that indicates which element of
the array is actually addressed.
• array: EQU 10h
•M OV X,3
• MOV A, [x+array]
This would have the effect of loading A with the fourth element
of the SRAM “array” that begins at address 0x10h. The fourth
element would be at address 0x13h.
7.0 Instruction Set Summary
Refer to the CY ASM Assemble r User’s Guid e for d etailed
information on these i nstructions. Note that conditional jump
instructions (i.e., JC, JNC, JZ, JNZ) take five cycles if jump is
taken, four cycles if no jump.
MNEMONIC
HALT
ADD A,expr
ADD A,[expr]
ADD A,[X+expr]
ADC A,expr
ADC A,[expr]
ADC A,[X+expr]
SUB A,expr
SUB A,[expr]
SUB A,[X+expr]
SBB A,expr
SBB A,[expr]
SBB A,[X+expr]
OR A,expr
OR A,[expr]
OR A,[X+expr]
AND A,expr
AND A,[expr]
AND A,[X+expr]
XOR A,expr
XOR A,[expr]
XOR A,[X+expr]
CMP A,expr
CMP A,[expr]
CMP A,[X+expr]
MOV A,expr
Operand
data
direct
index
data
direct
index
data
direct
index
data
direct
index
data
direct
index
data
direct
index
data
direct
index
data
direct
index
data
Opcode
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
Cycles
7
4
6
7
4
6
7
4
6
7
4
6
7
4
6
7
4
6
7
4
6
7
5
7
8
4
MNEMONIC
NOP
INC A
INC X
INC [expr]
INC [X+expr]
DEC A
DEC X
DEC [expr]
DEC [X+expr]
IORD expr
IOWR expr
POP A
POP X
PUSH A
PUSH X
SWAP A,X
SWAP A,DSP
MOV [expr],A
MOV [X+expr],A
OR [expr],A
OR [X+expr],A
AND [expr],A
AND [X+expr],A
XOR [expr],A
XOR [X+expr],A
IOWX [X+expr]
Operand
2
acc
x
direct
index
acc
x
direct
index
address
address
direct
index
direct
index
direct
index
direct
index
index
Opcode
0
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
Cycles
4
4
4
7
8
4
4
7
8
5
5
4
4
5
5
5
5
5
6
7
8
7
8
7
8
6
Document #: 38-08022 Rev. *C
Page 5 of 49
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FOR CY7C63722C
FOR
CY7C63723C
CY7C63743C
before the part executes code. See Section 10.1 for mo re
details.
1 = Disables the LVR circuit.
0 = Enables the LVR circuit.
Bit 2: Precision USB Clocking Enable
The Precision USB Clocking Enable only affects operation
in internal oscillator mode. In that mode, this bit must be
set to 1 to cause the internal clock to automatically pre-
cisely tune to USB timing requirements (6 MHz ±1.5%).
The frequency may have a looser initial tolerance at pow-
er-up, but all USB transmissions from the chip will meet the
USB specification.
1 = Enabled. The internal clock accuracy is 6 MHz ±1.5%
after USB traffic is received.
0 = Disabled. The internal clock accuracy is 6 MHz ±5%.
Bit 1: Internal Clock Output Disable
The Internal Clock Output Disable is used to keep the inter-
nal clock from driving out to the XTALOUT pin. This bit has
no effect in the external oscillator mode.
1 = Disab le internal clock output. XTALOUT pin will drive
HIGH.
0 = Enabl e the internal clock output. The internal clock is
driven out to the XTALOUT pin.
Bit 0: External Oscillator Enable
At power-up, the chip operates from the internal clock by
default. Setting the External Oscillator Enable bit HIGH dis-
ables the internal clock, and halts the part while the external
resonator/crystal oscillator is started. Clearing this bi t has
no immediate effect, although the state of this b it is used
when waking out of suspend mode to select between inter-
nal and external clock. In internal clock mode, XTALIN pin
will be configured as an inp ut with a weak pull-down and
can be used as a GPIO input (P2.1).
1 = Enable the external oscillator. The clock is switched to
external clock mode, as described in Section 9.1.
0 = Enable the internal oscillator.
9.1 Internal/External Oscillator Operation
The internal oscillator provides an operating clock, factory set
to a no minal frequency o f 6 MHz. T his clock req uires n o
external components. At power-up, the chip operates from the
internal clock. In this mode, the internal clock is buffered and
driven to th e XTALOUT pin by de fault, and the st ate of th e
XTALIN pin can be read at Port 2.1. While the internal clock is
enabled, its output can be disa bled at the XTALOUT pin by
setting the Interna l Clo ck Outpu t D isable bit of the C lock
Configuration Register.
Setting the External Oscillator Enable bit of the Clock Config-
uration Regi ster H IGH di sables the interna l clock, and hal ts
the p art whi le the externa l reson ator/crystal oscil lator is
started. Th e step s in volved in switching fro m Inte rnal to
External Clock mode are as follows:
1. At reset, chip begins operation using the internal clock.
2. Firmware sets Bit 0 of the Clock Configuration Register. For
example,
mov A, 1h
iowr F8h
; Set Bi t 0 HIGH (Externa l Oscil-
lator Ena ble bit). Bi t 7 clea red
gives faster start-up
; W rite to Clo ck Co nfiguration
Register
3. Internal clocking is halted, theinternal oscillator is disabled,
and the external clock oscillator is enabled.
4. After the external clock becomes stable, chip clocks are
re-enabled using the external clock signal. (Note that the
time for the external clock tobecome stable depends on the
external resonating device; see next section.)
5. After an additional delay the CPU is released to run. This
delay depends on the state ofthe Ext.Clock Resume Delay
bit of the Clock Configuration Register. The time is 128 µs
if the bit is 0, or 4 ms if the bit is 1.
6. Once the chip has been set to external oscillator, it can only
return to internal clock when waking from suspend mode.
Clearing bit 0 of the Clock Configuration Register will not
re-enable internal clock mode until suspend mode is
entered. See Section 11.0 for more details on suspend
mode operation.
If the Internal Clock is enabled, the XTALIN pin can serve as
a general purpose input, and its state can be read at Port 2,
Bit 1 (P2.1). Refer to Figure 12-8 for the Port 2 Data Register.
In this mode, there is a weak pull-down at the XTALIN pin. This
input cannot provide an interrupt source to the CPU.
9.2 External Oscillator
The user can conn ect a low-cost cera mic reso nator or an
external oscillator to the XTALIN/XTALOUT pins to provide a
precise reference fre quency for the chip clock, as show n in
Figure 9-1. The external components required are a ceramic
resonator or crystal and an y associated cap acitors. To run
from the external resonator, the External Oscillator Enable bit
of the Cl ock Co nfiguration R egister must be set to 1, as
explained in the previous section.
Start-up times for the externa l o scillator depend on the
resonating device . Ceramic resona tor base d oscillators
typically start in les s than 100 µs, while crystal based oscil-
lators t ake lon ger, typical ly 1 to 10 ms. Board cap acitance
should be minimize d on the XTALIN and XTALOUT pins by
keeping the traces as short as possible.
An external 6-MHz clock can be applied to the XTALIN pin if
the XTALOUT pin is left open.
10.0 Reset
The USB Controller supports three types of resets. The effects
of the reset are listed below. The reset types are:
1. Low-voltage Reset (LVR)
2. Brown Out Reset (BOR)
3. Watchdog Reset (WDR)
The occurrence of a reset is recorded in the Processor Status
and Con trol Reg ister ( Figure 20-1). Bit s 4 (L ow-voltage or
Brown-out Reset bit) and 6 (Watchdog Reset bit) are used to
record the occurrence of L VR/BOR an d WD R respectivel y.
The firmware can interrogate these bits to determine the cause
of a reset.
Document #: 38-08022 Rev. *C
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| PDF Descargar | [ Datasheet CY7C63723C.PDF ] | |
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