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PDF LPC1519JBD64 Data sheet ( Hoja de datos )
| Número de pieza | LPC1519JBD64 | |
| Descripción | 32-bit ARM Cortex-M3 microcontroller | |
| Fabricantes | NXP Semiconductors | |
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LPC15xx
32-bit ARM Cortex-M3 microcontroller; up to 256 kB flash and
36 kB SRAM; FS USB, CAN, RTC, SPI, USART, I2C
Rev. 1 — 19 February 2014
Product data sheet
1. General description
The LPC15xx are ARM Cortex-M3 based microcontrollers for embedded applications
featuring a rich peripheral set with very low power consumption. The ARM Cortex-M3 is a
next generation core that offers system enhancements such as enhanced debug features
and a higher level of support block integration.
The LPC15xx operate at CPU frequencies of up to 72 MHz. The ARM Cortex-M3 CPU
incorporates a 3-stage pipeline and uses a Harvard architecture with separate local
instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3
CPU also includes an internal prefetch unit that supports speculative branching.
The LPC15xx includes up to 256 kB of flash memory, 32 kB of ROM, a 4 kB EEPROM,
and up to 36 kB of SRAM. The peripheral compliment includes one full-speed USB 2.0
device, two SPI interfaces, three USARTs, one Fast-mode Plus I2C-bus interface, one
C_CAN module, PWM/timer subsystem with four configurable, multi-purpose State
Configurable Timers (SCTimer/PWM) with input pre-processing unit, a Real-time clock
module with independent power supply and a dedicated oscillator, two 12-channel/12-bit,
2 Msamples/s ADCs, one 12-bit, 500 kSamples/s DAC, four voltage comparators with
internal voltage reference, and a temperature sensor. A DMA engine can service most
peripherals.
For additional documentation related to the LPC15xx parts, see Section 17 “References”.
2. Features and benefits
System:
ARM Cortex-M3 processor (version r2p1), running at frequencies of up to 72 MHz.
ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
System tick timer.
Serial Wire Debug (SWD) with four breakpoints and two watchpoints.
Single-cycle multiplier supported.
Memory Protection Unit (MPU) included.
Memory:
Up to 256 kB on-chip flash programming memory with 256 Byte page write and
erase.
Up to 36 kB SRAM.
4 kB EEPROM.
http://www.Datasheet4U.com
1 page  
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
4.1 Ordering options
Table 2. Ordering options for LPC15xx
Type number
Flash/ EEPROM/ Total USB USART I2C SPI C_CAN SCTimer/ 12-bit DAC GPIO
kB kB
SRAM/
PWM
ADC0/1
kB channels
LPC1549JBD100 256 4
36 yes 3
12 1
4
12/12
1 76
LPC1549JBD64 256 4
36 yes 3
12 1
4
12/12
1 44
LPC1549JBD48 256 4
36 yes 3
12 1
4
9/7 1 30
LPC1548JBD100 128 4
20 yes 3
12 1
4
12/12
1 76
LPC1548JBD64 128 4
20 yes 3
12 1
4
12/12
1 44
LPC1547JBD64 64
4
12 yes 3
12 1
4
12/12
1 44
LPC1547JBD48 64
4
12 yes 3
12 1
4
9/7 1 30
LPC1519JBD100 256 4
36 no 3
12 1
4
12/12
1 78
LPC1519JBD64 256 4
36 no 3
12 1
4
12/12
1 46
LPC1518JBD100 128 4
20 no 3
12 1
4
12/12
1 78
LPC1518JBD64 128 4
20 no 3
12 1
4
12/12
1 46
LPC1517JBD64 64
4
12 no 3
12 1
4
12/12
1 46
LPC1517JBD48 64
4
12 no 3
12 1
4
9/7 1 32
LPC15XX
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 19 February 2014
© NXP B.V. 2014. All rights reserved.
5 of 99
5 Page 
NXP Semiconductors
LPC15xx
32-bit ARM Cortex-M3 microcontroller
PIO0_22 49
PIO0_23 50
PIO1_7 51
VDD 52
PIO1_8 53
PIO1_9 54
VSS 55
VSS 56
VDD 57
PIO0_24 58
PIO1_10 59
PIO0_25 60
PIO0_26 61
PIO0_27 62
PIO0_28 63
PIO0_29 64
LPC1519JBD64
LPC1518JBD64
LPC1517JBD64
32 PIO0_16
31 PIO0_15
30 PIO0_14
29 PIO0_13
28 PIO1_3
27 VSS
26 VSS
25 PIO1_2
24 PIO0_12
23 PIO0_11
22 VDD
21 VSSA
20 VDDA
19 PIO0_10
18 VREFP_DAC_VDDCMP
17 PIO0_18
Fig 7. LQFP64 pin configuration (without USB)
aaa-009376
76 50
LPC1548JBD100
LPC1518JBD100
100 26
Fig 8. LQFP100 pin configuration
aaa-009351
LPC15XX
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 19 February 2014
© NXP B.V. 2014. All rights reserved.
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