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PDF IT66121FN Data sheet ( Hoja de datos )
| Número de pieza | IT66121FN | |
| Descripción | Low Power Transmitter | |
| Fabricantes | ITE TECH | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de IT66121FN (archivo pdf) en la parte inferior de esta página. Total 39 Páginas | ||
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IT66121FN
Low Power Transmitter with HDMI1.4 3D
Preliminary Datasheet
Specification V0.99
ITE TECH. INC.
www.ite.com.tw
Nov-2011 Rev:0.99
1/39
http://www.Datasheet4U.com
1 page  
IT66121FN
Pin Description
Digital Video Input Pins
Pin Name Direction Description
D[23:0]
Input
Digital video input pins.
DE
HSYNC
VSYNC
PCLK
Input
Input
Input
Input
Data enable
Horizontal sync. signal
Vertical sync. signal
Input data clock
Digital Audio Input Pins
Pin Name
SCK/MCLK
WS
I2S0
I2S1
I2S2
I2S3/SPDIF
Direction
Input
Input
Input
Input
Input
Input
Description
I2S serial clock input /SPDIF master clock input
I2S word select input
I2S 0 serial data input
I2S 1 serial data input
I2S 2 serial data input
I2S 3 serial data input /SPDIF audio input
HDMI Interface Pins
Pin Name Direction
CEC
I/O
DDCSCL
I/O
DDCSDA
I/O
HPD
Input
Description
CEC signal (5V-tolerant)
I2C Clock for DDC (5V-tolerant)
I2C Data for DDC (5V-tolerant)
Hot Plug Detection (5V-tolerant)
TMDS front-end interface pins
Pin Name Direction Description
TX2P
Analog HDMI Channel 2 positive output
TX2M
Analog HDMI Channel 2 negative output
TX1P
Analog HDMI Channel 1 positive output
TX1M
Analog HDMI Channel 1 negative output
TX0P
Analog HDMI Channel 0 positive output
TX0M
Analog HDMI Channel 0 negative output
TXCP
Analog HDMI Clock Channel positive output
www.ite.com.tw
Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Pin No.
36-50,
52-55,
57-61
62
63
64
51
Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
Pin No.
7
6
5
4
3
2
Type
Schmitt
Schmitt
Schmitt
LVTTL
Pin No.
17
16
15
14
Type
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
TMDS
Pin No.
30
29
27
26
25
24
22
Nov-2011 Rev:0.99 5/39
5 Page 
IT66121FN
High-Bit-Rate (HBR) Audio is first introduced in the HDMI 1.3 standard. It is called upon by high-end
audio system such as DTS-HD and Dolby TrueHD. No specific interface is defined by the HBR
standard. The IT66121 supports HBR audio in two ways. One is to employ the four I2S inputs
simultaneously, where the original streaming HBR audio is broken into four parallel data streams
before entering the IT66121. The other is to use the S/PDIF input port. Since the data rate here is as
high as 98.304Mbps, a coherent MCLK is required in this application.
Interrupt Generation
The system micro-controller should take in the interrupt signal output by IT66121 at PIN 10 (INT). INT
pin can be configured as Push-pull or Tristate mode depending on user’s application. IT66121
generates an interrupt signal with events involving the following signals or situations:
1. Hot-plug detection (Pin 14, HPD) experiences state changes.
2. Receiver detection circuit reports the presence or absence of an active termination at the TMDS
Clock Channel (RxSENDetect)
3. DDC bus is hanged for any reasons
4. Audio FIFO overflows
5. HDCP authentication fails
6. Audio/Video data is stable or not
A typical initialization of HDMI link should be based on interrupt signal and appropriate register probing.
Recommended flow is detailed in IT66121 Programming Guide. Simply put, the microcontroller should
monitor the HPD status first. Upon valid HPD event, move on to check RxSENDetect register to see if
the receiver chip is ready for further handshaking. When RxSENDetect is asserted, start reading EDID
data through DDC channels and carry on the rest of the handshaking subsequently.
If the micro-controller makes no use of the interrupt signal as well as the above-mentioned status
registers, the link establishment might fail. Please do follow the suggested initialization flow
recommended in IT66121 Programming Guide.
www.ite.com.tw
Nov-2011 Rev:0.99 11/39
11 Page | ||
| Páginas | Total 39 Páginas | |
| PDF Descargar | [ Datasheet IT66121FN.PDF ] | |
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