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24LC21A-PのメーカーはMicrochipTechnologyです、この部品の機能は「1K2.5VDualModeI2CSerialEEPROM」です。 |
部品番号 | 24LC21A-P |
| |
部品説明 | 1K2.5VDualModeI2CSerialEEPROM | ||
メーカ | MicrochipTechnology | ||
ロゴ | |||
このページの下部にプレビューと24LC21A-Pダウンロード(pdfファイル)リンクがあります。 Total 16 pages
24LC21A
1K 2.5V Dual Mode I2C™ Serial EEPROM
FEATURES
• Single supply with operation down to 2.5V
• Completely implements DDC1™/DDC2™
interface for monitor identification, including recov-
ery to DDC1
• Pin and function compatible with 24LC21
• Low power CMOS technology
- 1 mA typical active current
- 10 µA standby current typical at 5.5V
• 2-wire serial interface bus, I2C™ compatible
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to eight bytes
• 10,000,000 erase/write cycles guaranteed
• Data retention > 200 years
• ESD Protection > 4000V
• 8-pin PDIP and SOIC package
• Available for extended temperature ranges
- Commercial (C):
0°C to +70°C
- Industrial (I):
-40°C to +85°C
DESCRIPTION
The Microchip Technology Inc. 24LC21A is a 128 x 8-
bit dual-mode Electrically Erasable PROM. This device
is designed for use in applications requiring storage
and serial transmission of configuration and control
information. Two modes of operation have been imple-
mented: Transmit-Only Mode and Bi-directional Mode.
Upon power-up, the device will be in the Transmit-Only
Mode, sending a serial bit stream of the memory array
from 00h to 7Fh, clocked by the VCLK pin. A valid high
to low transition on the SCL pin will cause the device to
enter the transition mode, and look for a valid control
byte on the I2C bus. If it detects a valid control byte from
the master, it will switch into Bi-directional Mode, with
byte selectable read/write capability of the memory
array using SCL. If no control byte is received, the
device will revert to the Transmit-Only Mode after it
receives 128 consecutive VCLK pulses while the SCL
pin is idle. The 24LC21A is available in a standard 8-pin
PDIP and SOIC package in both commercial and
industrial temperature ranges.
PACKAGE TYPES
PDIP
NC 1
NC 2
NC 3
VSS 4
SOIC
8 VCC
7 VCLK
6 SCL
5 SDA
NC 1
NC 2
NC 3
VSS 4
BLOCK DIAGRAM
8 VCC
7 VCLK
6 SCL
5 SDA
HV GENERATOR
I/O
CONTROL
LOGIC
MEMORY
CONTROL
LOGIC
XDEC
SDA SCL
VCLK
VCC
VSS
EEPROM
ARRAY
PAGE LATCHES
YDEC
SENSE AMP
R/W CONTROL
DDC is a trademark of the Video Electronics Standards Association.
I2C is a trademark of Philips Corporation.
© 1996 Microchip Technology Inc.
Preliminary
This document was created with FrameMaker 4 0 4
DS21160B-page 1
1 Page 24LC21A
TABLE 1-3: AC CHARACTERISTICS
Parameter
Vcc= 2.5-5.5V Vcc= 4.5 - 5.5V
Symbol Standard Mode
Fast Mode
Units
Remarks
Min Max Min Max
Clock frequency
FCLK — 100 — 400 kHz
Clock high time
THIGH 4000
—
600
—
ns
Clock low time
TLOW 4700 — 1300 —
ns
SDA and SCL rise time
TR
—
1000
—
300
ns (Note 1)
SDA and SCL fall time
TF — 300 — 300 ns (Note 1)
START condition hold time THD:STA 4000
—
600
—
ns After this period the first clock
pulse is generated
START condition setup
TSU:STA 4700
—
600
—
time
ns Only relevant for repeated
START condition
Data input hold time
THD:DAT
0
—
0
— ns (Note 2)
Data input setup time
TSU:DAT 250 — 100 —
ns
STOP condition setup time TSU:STO 4000
—
600
—
ns
Output valid from clock
TAA
—
3500
—
900
ns (Note 2)
Bus free time
TBUF
4700
—
1300
—
ns Time the bus must be free
before a new transmission
can start
Output fall time from VIH
minimum to VIL maximum
TOF
—
250 20 + 250
ns (Note 1), CB ≤ 100 pF
0.1 CB
Input filter spike suppres- TSP — 50 — 50 ns (Note 3)
sion (SDA and SCL pins)
Write cycle time
TWR
—
10
—
10 ms Byte or Page mode
Transmit-Only Mode Parameters
Output valid from VCLK
TVAA
— 2000 — 1000 ns
VCLK high time
TVHIGH 4000
—
600
—
ns
VCLK low time
TVLOW 4700 — 1300 —
ns
VCLK setup time
TVHST
0
—
0
— ns
VCLK hold time
TSPVL 4000
—
600
—
ns
Mode transition time
TVHZ — 1000 — 500 ns
Transmit-Only power up
TVPU
0
—
0
— ns
time
Input filter spike suppres- TSPV — 100 — 100 ns
sion (VCLK pin)
Endurance
— 10M — 10M — cycles 25°C, Vcc = 5.0V, Block Mode
(Note 4)
Note 1: Not 100% tested. CB = Total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to Schmitt trigger inputs which provide noise and spike
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
© 1996 Microchip Technology Inc.
Preliminary
DS21160B-page 3
3Pages 24LC21A
FIGURE 3-3: DISPLAY OPERATION PER DDC STANDARD PROPOSED BY VESA
Display Power-on
or
DDC Circuit Powered
from +5 volts
Communication
is idle
The 24LC21A was designed to
comply to the portion of flowchart inside dash box
Is Vsync
present?
Yes
Send EDID continuously
using Vsync as clock
No
High to low
transition on
SCL?
No
High to low
transition on
SCL?
Yes
Stop sending EDID.
Switch to DDC2 mode.
No
Display has
optional
transition state
?
Yes
Set Vsync counter = 0
or start timer
No
Yes
DDC2 communication
idle. Display waiting for
address byte.
DDC2B
address
received?
No
Yes
Receive DDC2B
command
No
No
Change on
SCL, SDA or
VCLK lines?
Yes
High - low
transition on SCL
?
Yes
Reset Vsync counter = 0
Valid
DDC2 address
received?
Reset counter or timer
Is display
Access.busTM
capable?
Yes
Valid Access.bus
address?
Yes
Yes
Respond to DDC2B
command
No
No
No
No VCLK
cycle?
Yes
Increment VCLK counter
(if appropriate)
See Access.bus
specification to determine
correct procedure.
No Counter=128 or
timer expired?
Yes
Switch back to DDC1
mode.
Note 1: The base flowchart is copyright © 1993, 1994, 1995 Video Electronic Standard Association (VESA) from
VESA’s Display Data Channel (DDC) Standard Proposal ver. 2p rev. 0, used by permission of VESA.
2: The dash box and text “The 24LC21A and... inside dash box.” are added by Microchip Technology, Inc.
3: Vsync signal is normally used to derive a signal for VCLK pin on the 24LC21A.
DS21160B-page 6
Preliminary
© 1996 Microchip Technology Inc.
6 Page | |||
ページ | 合計 : 16 ページ | ||
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PDF ダウンロード | [ 24LC21A-P データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
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