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PDF ISL6615A Data sheet ( Hoja de datos )
| Número de pieza | ISL6615A | |
| Descripción | High-Frequency 6A Sink Synchronous MOSFET Drivers | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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High-Frequency 6A Sink Synchronous MOSFET
Drivers with Protection Features
ISL6615A
The ISL6615A is a high-speed MOSFET driver optimized
to drive upper and lower power N-Channel MOSFETs in a
synchronous rectified buck converter topology. This
driver, combined with an Intersil Digital or Analog
multiphase PWM controller, forms a complete high
frequency and high efficiency voltage regulator.
The ISL6615A drives both upper and lower gates over a
range of 4.5V to 13.2V. This drive-voltage provides the
flexibility necessary to optimize applications involving
trade-offs between gate charge and conduction losses.
The ISL6615A features 6A typical sink current for the
low-side gate driver, enhancing the lower MOSFET gate
hold-down capability during PHASE node rising edge,
preventing power loss caused by the self turn-on of the
lower MOSFET due to the high dV/dt of the switching
node.
An advanced adaptive zero shoot-through protectionis
integrated to prevent both the upper and lower MOSFETs
from conducting simultaneously and to minimize the
dead-time. The ISL6615A includes an overvoltage
protection feature opear tional before VCC exceeds its
turn-on threshold,at which the PHASE node is connected
to the gate of the low side MOSFET (GL ATE). The output
voltage of the converter is then limited by the threshold
of the low side MOSFET, which provides some protection
to the load if the upper MOSFET(s) is shorted.
The ISL6615A also features aninput that recognizes a
high-impedance state, working together with Intersil
multiphase PWM controllers to prevennt egative
transients on the controlled outputvoltage when
operation is suspended. Thsi feature eliminates the need
for the Schottkydiode that may be utilized in apower
system to protect the load from negative output voltage
damage.
Features
• Dual MOSFET Drives for Synchronous Rectified
Bridge
• Advanced Adaptive Zero Shoot-Through Protection
- Body Diode Detection
-L GATE Detection
-A uto-zero of rDS(ON) Conduction Offset Effect
• Adjustable Gate Voltage for Optimal Efficiency
• 36V Internal Bootstrap Schottky Diode
• Bootstrap Capacitor Overcharging Prevention
• Supports High Switching Frequency (up to 1MHz)
- 6A LGATE Sinking Current Capability
- Fast Rise/Fall Times and Low Propagation Delays
• Support 5V PWM Input Logic
• Tri-State PWM Input for Safe Output StageShutdown
• Tri-State PWM Input Hysteresis for Applications with
Power Sequencing Requirement
• Pre-POR Overvoltage Protection
• VCC Undervoltage Protection
• Expandable Bottom Copper PAD for Better Heat
Spreading
• Dual Flat No-Lead (DFN) Package
- Near Chip-Scale Package Footprint; Improves PCB
Efficiency and Thinner in Profile
• Pb-free (RoHS compliant)
Applications*(see page 10)
• Optimized for POL DC/DC Converters for IBA
Systems
• Core Regulators for Intel® and AMD®
Microprocessors
• High Current Low-Profile DC/DC Converters
• High Frequency and High Efficiency VRM and VRD
• Synchronous Rectification for Isolated Power
Supplies
Related Literature*(see page 10)
Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface MountDevices
(SMDs)”
Technical Brief TB389 “PCB Land Pattern Design and
Surface Mount Guidelines for QNF Packages”
April 22, 201 0
FN6608 .1
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
http://www.Datasheet4U.com
Copyright Intersil Americas Inc. 2008, 2010. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6615A
Electrical Specifications Recommended Operating Conditions; Boldface limits apply over the operating
temperature ranges. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
(Note 8) TYP (Note 8) UNITS
UGATE Rise Time (Note 9)
tRU VPVCC = 12V, 3nF Load, 10% to 90% - 13 -
LGATE Rise Time (Note 9)
tRL VPVCC = 12V, 3nF Load, 10% to 90% - 10 -
UGATE Fall Time (Note 9)
tFU VPVCC = 12V, 3nF Load, 90% to 10% - 10 -
LGATE Fall Time (Note 9)
tFL VPVCC = 12V, 3nF Load, 90% to 10% - 10 -
UGATE Turn-On Propagation Delay
(Note 9)
tPDHU VPVCC = 12V, 3nF Load, Adaptive
- 30 -
ns
ns
ns
ns
ns
LGATE Turn-On Propagation Delay
(Note 9)
tPDHL VPVCC = 12V, 3nF Load, Adaptive
- 20 -
ns
UGATE Turn-Off Propagation Delay
(Note 9)
tPDLU VPVCC = 12V, 3nF Load
- 10 -
ns
LGATE Turn-Off Propagation Delay
(Note 9)
tPDLL
VPVCC = 12V, 3nF Load
- 20 -
ns
LG/UG Tri-State Propagation Delay
(Note 9)
tPDTS VPVCC = 12V, 3nF Load
- 20 -
ns
OUTPUT (Note 9)
Upper Drive Source Current
IU_SOURCE VPVCC = 12V, 3nF Load
- 2.5 -
A
Upper Drive Source Impedance
RU_SOURCE 150mA Source Current
-1-
Ω
Upper Drive Sink Current
IU_SINK VPVCC = 12V, 3nF Load
-4-
A
Upper Drive Sink Impedance
RU_SINK 150mA Sink Current
- 0.8 -
Ω
Lower Drive Source Current
IL_SOURCE VPVCC = 12V, 3nF Load
-4-
A
Lower Drive Source Impedance
RL_SOURCE 150mA Source Current
- 0.7 -
Ω
Lower Drive Sink Current
IL_SINK VPVCC = 12V, 3nF Load
-6-
A
Lower Drive Sink Impedance
RL_SINK 150mA Sink Current
- 0.45 -
Ω
NOTES:
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
9. Limits established by characterization and are not production tested.
5 FN6608.1
April 22, 2010
5 Page 
Package Outline Drawing
L10.3x3
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 6, 09/09
3.00
ISL6615A
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
1
2
(4X) 0.10
TOP VIEW
PACKAGE
OUTLINE
(10x 0.23)
(10 x 0.55)
10 x 0.23 4
0.415
0.23
0.35
0.20
1.60
BOTTOM VIEW
10x 0.35
4
(4X) 0.10 M C A B
SIDE VIEW
SEE DETAIL "X"
0.10 C
C
BASE PLANE
SEATING PLANE
0.08 C
(8x 0.50)
1.60
TYPICAL RECOMMENDED LAND PATTERN
C 0.20 REF 5
0.05
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Lead width applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
11 FN6608.1
April 22, 2010
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet ISL6615A.PDF ] | |
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