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PDF CS470XX Data sheet ( Hoja de datos )
| Número de pieza | CS470XX | |
| Descripción | Audio SOC Processor | |
| Fabricantes | Cirrus Logic | |
| Logotipo |  |
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CS470xx
CS470xx Data Sheet
Features
The CS470xx family is a new generation of audio
system-on-a-chip (ASOC) processors targeted at high
Cost-effective, High-performance 32-bit DSP
fidelity, cost sensitive designs. Derived from the highly
300,000,000 MAC/S (multiply accumulates per second)
successful CS48500 32-bit fixed-point audio enhancement
processor family, the CS470xx further simplifies system
Dual MAC cycles per clock
design and reduces total system cost by integrating the S/
72-bit accumulators are the highest precision in the
industry
32K x 32-bit SRAM with three 2K blocks assignable to
either Y data or program memory
PDIF Rx, S/PDIF Tx, analog inputs, analog outputs, and
SRCs. For example, a hardware SRC can down-sample a
192 kHz S/PDIF stream to a lower Fs to reduce memory
and MIPS requirements for processing. This integration
effectively reduces the chip count from 3 to 1, which allows
Integrated DAC and ADC Functionality
smaller, less expensive board designs.
8† Channels of 24-bit DAC output: 108dB DR, –98 dB
THD+N
4† Channels of 24-bit ADC input: 105dB DR, –98 dB
THD+N
Target applications include:
Automotive head units and outboard amplifiers
Automotive processors and automotive integration hubs
Integrated 5:1 analog mux feeds one stereo ADC
Digital TV
Configurable Serial Audio Inputs and Outputs
MP3 docking stations
Integrated 192 kHz S/PDIF Rx
Integrated 192 kHz S/PDIF Tx
Supports 32-bit serial data @ 192 kHz
Supports 32-bit audio sample I/O between DSP chips
TDM I/O modes
Supports Different Sample Rates (Fs)
Three integrated hardware SRC blocks
Output can be master or slave
Supports dual-domain Fs on S/PDIF vs. I²S inputs
DSP Tool Set with Private Keys Protect Customer IP
Integrated Clock Manager/PLL
Flexibility to operate from internal PLL, external crystal,
external oscillator
Input Fs Auto Detection w/ µC Acknowledgement
AVR and DVD RX
DSP controlled speakers (subwoofers, sound bars)
The CS470xx is programmed using the simple yet powerful
Cirrus proprietary DSP Composer™ GUI development and
pre-production tuning tool. Processing chains can be
designed using a drag-and-drop interface to place/utilize
functional macro audio DSP primitives and custom audio
filtering blocks. The end result is a software image that is
downloaded to the DSP via serial control port.
The Cirrus Framework™ programming environment offers
Assembly and C language compilers and other software
development tools for porting existing code to the CS470xx
family platform.
The CS470xx is available in a 100-pin LQFP package with
exposed pad for better thermal characteristics. Both
Commercial (0°C to +70°C) and Automotive (–40°C to
+85°C) temperature grades.
Host Control and Boot via I²C™ or SPI™ Serial Interface Ordering Information:
Configurable GPIOs and External Interrupt Input
See Section 6 for ordering information.
1.8V Core and a 3.3V I/O that is tolerant to 5V input
Low-power Mode
“†” features differ on CS47024, CS47028, or CS47048.
See Table 3-1.
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2012
(All Rights Reserved)
DS787PP9
JUL '12
1 page  
3 Code Overlays
3 Code Overlays
The suite of software available for the CS470xx family consists of an operating system (OS) and a library of overlays. The
software components for the CS470xx family include:
1. OS/Kernel—Encompasses all non-audio processing tasks, including loading data from external serial memory,
processing host messages, calling audio-processing subroutines, error concealment, etc.
2. Decoder—Any module that performs a compressed audio decode on IEC61937-packed data delivered via S/PDIF
Rx or I²S input, such as Dolby Digital (AC3).
3. Matrix-processor—Any Module that performs a matrix decode on PCM data to produce more output channels than
input channels (2Æn channels). Examples are Dolby® Pro Logic® IIx and SRS Circle Surround II®. Generally
speaking, these modules increase the number of valid channels in the audio I/O buffer.
4. Virtualizer-processor—Any module that encodes PCM data into fewer output channels than input channels (nÆ2
channels) with the effect of providing “phantom” speakers to represent the physical audio channels that were
eliminated. Examples are Dolby Headphone® 2 and Dolby® Virtual Speaker® 2. Generally speaking, these
modules reduce the number of valid channels in the audio I/O buffer.
5. Post-processors—Any module that processes audio I/O buffer PCM data. Examples are bass management, audio
manager, tone control, EQ, delay, customer-specific effects, and any post-processing algorithms available for the
CS470xx DSP.
The bulk of standard overlays are stored in ROM within the CS470xx, but a small image is required to configure the
overlays and boot the DSP. This small image can either be stored in an external serial flash/EEPROM, or downloaded via
a host controller through the SPI/I²C serial port.
The overlay structure reduces the time required to reconfigure the DSP when a processing change is requested. Each
overlay can be reloaded independently without disturbing the other overlays. For example, when a different post-processor
is selected, the OS, does not need to be reloaded—only the new post-processor.
Table 3-1 lists the different configuration options available. Refer to the CS470xx Firmware User’s Manual for the latest
listing of application codes and Cirrus Framework™ modules available. See Table 3-2, which provides a summary of the
available channels for each type of input and output communication mode for members of the CS470xx family of DSPs.
5 DS787PP9
5 Page 
4.4 DSP I/O Description
4.3.8 Serial Control Port (I2C or SPI)
The on-chip serial control port is capable of operating as master or slave in either SPI or I2C modes. Master/Slave
operation is chosen by mode select pins when the CS470xx comes out of reset. The serial clock pin can support
frequencies as high as 25 MHz in SPI mode (SPI clock speed must always be < (DSP Core Frequency/2)). The CS470xx
serial control port also includes a pin for flow control of the communications interface (SCP_BSY) and a pin to indicate
when the DSP has a message for the host (SCP_IRQ).
4.3.9 GPIO
Many of the CS470xx peripheral pins are multiplexed with GPIO. Each GPIO can be configured as an output, an input, or
an input with interrupt. Each input-pin interrupt can be configured as rising edge, falling edge, active-low, or active-high.
4.3.10 PLL-based Clock Generator
The low-jitter PLL generates integer or fractional multiples of a reference frequency, which is used to clock the DSP core
and peripherals. Through a second PLL divider chain, a dependent clock domain can be output on the DAO port for driving
audio converters. The CS470xx defaults to running from the external reference frequency and is switched to use the PLL
output after overlays have been loaded and configured, either through master boot from an external flash or through host
control. A built-in crystal oscillator circuit with a buffered output is provided. The buffered output frequency ratio is
selectable between 1:1 (default) or 2:1.
4.3.11 Hardware Watchdog Timer
The CS470xx has an integrated watchdog timer that acts as a “health” monitor for the DSP. The watchdog timer must be
reset by the DSP before the counter expires, or the entire chip is reset. This peripheral ensures that the CS470xx resets
itself in the event of a temporary system failure. In stand-alone mode (where there is no host MCU), the DSP reboots from
external flash. In slave mode (where the host MCU is present), a GPIO is used to signal the host that the watchdog has
expired and the DSP should be rebooted and re-configured.
4.4 DSP I/O Description
4.4.1 Multiplexed Pins
Many of the CS470xx pins are multifunctional. For details on pin functionality, see Section 10.5, “Pin Assignments”, in the
CS470xx Hardware User’s Manual.
4.4.2 Termination Requirements
Open-drain pins on the CS470xx must be pulled high for proper operation. See the CS470xx Hardware User’s Manual to
identify which pins are open-drain and what value of pull-up resistor is required for proper operation.
Mode select pins on CS470xx are used to select the boot mode on the rising edge from reset. A detailed explanation of
termination requirements for each communication mode select pin can be found in the CS470xx Hardware User’s Manual.
4.4.3 Pads
The CS470xx Digital I/Os operate from the 3.3 V supply and are 5 V tolerant.
4.5 Application Code Security
The external program code can be encrypted by the programmer to protect any intellectual property it contains. A secret,
customer-specific key is used to encrypt the program code that is to be stored external to the device. Contact your local
Cirrus representative for details.
11 DS787PP9
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CS470XX.PDF ] | |
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