PDF IS25LQ080 Data sheet ( Hoja de datos )

Número de pieza	IS25LQ080
Descripción	8Mbit Single Operating Voltage Serial Flash Memory
Fabricantes	ISSI
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No Preview Available ! 8 Mbit Single Operating Voltage Serial Flash Memory With 104 MHz Dual- or 100MHz Quad-Output SPI Bus Interface IS25LQ080 FEATURES • Single Power Supply Operation - Low voltage range: 2.3 V - 3.6 V • Memory Organization - IS25LQ080: 1024K x 8 (8 Mbit) • Cost Effective Sector/Block Architecture - 8Mb : Uniform 4KByte sectors / sixteen uniform 64KByte blocks • Serial Peripheral Interface (SPI) Compatible - Supports single-, dual- or quad-output - Supports SPI Modes 0 and 3 - Maximum 33 MHz clock rate for normal read - Maximum 104 MHz clock rate for fast read - Maximum 208MHz clock rate - Maximum 400MHz clock rate equivalent Quad SPI • Byte Program Operation - Typical 10 us/Byte • Page Program (up to 256 Bytes) Operation - Maximum 0.7ms per page program • Sector, Block or Chip Erase Operation - Sector Erase (4KB)150ms (Typ) - Block Erase (64KB)500ms (Typ) - Chip Erase 2s (8Mb) • Low Power Consumption - Max 12 mA active read current - Max 20 mA program/erase current - Max 30 uA standby current • Hardware Write Protection - Protect and unprotect the device from write operation by Write Protect (WP#) Pin • Software Write Protection - The Block Protect (BP3, BP2, BP1, BP0) bits allow partial or entire memory to be configured as read-only • High Product Endurance - Guaranteed 100,000 program/erase cycles per single sector - Minimum 20 years data retention • Industrial Standard Pin-out and Package - 8-pin 208mil SOIC - 8-pin 150mil VVSOP - 8-contact WSON - PDIP - Lead-free (Pb-free) package •Additional 256-byte Security information one-time programmable (OTP) area •Special protect function - Safe guard function (Appendix 1) - Sector unlock function (Appendix 2) GENERAL DESCRIPTION The IS25LQ080 is 8 Mbit Serial Peripheral Interface (SPI) Flash memories, providing single-, dual or quad- output. The devices are designed to support a 33 MHz fclock rate in normal read mode, and 104 MHz in fast read (Quad output is 100MHz), the fastest in the industry. The devices use a single low voltage power supply, ranging from 2.3 Volt to 3.6 Volt, to perform read, erase and program operations. The devices can be programmed in standard EPROM programmers. The IS25LQ080 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output (Sl), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in one program operation. These devices are divided into uniform 4 KByte sectors or uniform 64 KByte blocks. The IS25LQ080 are offered in 8-pin SOIC 208mil, 8-pin PDIP, 8-pin VVSOP and 8-contact WSON. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 10/18/2012 1 1 page IS25LQ080 SPI MODES DESCRIPTION Multiple IS25LQ080 devices can be connected on the SPI serial bus and controlled by a SPI Master, i.e. microcontroller, as shown in Figure 1. The devices support either of two SPI modes: Mode 0 (0, 0) Mode 3 (1, 1) The difference between these two modes is the clock polarity when the SPI master is in Stand-by mode: the serial clock remains at “0” (SCK = 0) for Mode 0 and the clock remains at “1” (SCK = 1) for Mode 3. Please refer to Figure 2. For both modes, the input data is latched on the rising edge of Serial Clock (SCK), and the output data is available from the falling edge of SCK. Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices) SPI Interface with (0,0) or (1,1) SDI SDI SCK SPI Master (i.e. Microcontroller) CS3 CS2 CS1 SCK SO SI SCK SO SI SCK SO SI SPI Memory Device CE# WP# HOLD# SPI Memory Device CE# WP# HOLD# SPI Memory Device CE# WP# HOLD# Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as appropriate. Figure 2. SPI Modes Supported SCK Mode 0 (0,0) SCK Mode 3 (1,1) SI Input mode SO MSb Integrated Silicon Solution, Inc.- www.issi.com Rev. A 10/18/2012 MSb 5 5 Page Table 11. Instruction Set IS25LQ080 Instruction Name RDID JEDEC ID READ RDMDID WREN WRDI RDSR WRSR READ FAST_READ FRDO FRDIO FRQO FRQIO MR PAGE_ PROG SECTOR_ER BLOCK_ER (64KB) CHIP_ER Quad page program Program/Erase suspend Program/Erase resume Program information Raw Read information Raw Hex Code ABh 9Fh 90h 06h 04h 05h 01h 03h 0Bh 3Bh BBh 6Bh EBh FFh 02h D7h/ 20h D8h C7h/ 60h 32h 75h /B0h 7Ah /30h B1h 4Bh Operation Read Manufacturer and Product ID Read Manufacturer and Product ID by JEDEC ID Command Read Manufacturer and Device ID Write Enable Write Disable Read Status Register Write Status Register Read Data Bytes from Memory at Normal Read Mode Read Data Bytes from Memory at Fast Read Mode Fast Read Dual Output Fast Read Dual I/O Fast Read Quad Output Fast Read Quad I/O Mode Reset Page Program Data Bytes Into Memory Sector Erase Block Erase 64K byte Chip Erase Page Program Data Bytes Into Memory with Quad interface Suspend during the program/erase Resume program/erase Program 256 bytes of Security area Read 256 bytes of Security area Comman d Cycle 4 Bytes 1 Byte 4 Bytes 1 Byte 1 Byte 1 Byte 2 Bytes 4 Bytes 5 Bytes 5 Bytes 3 Bytes 5 Bytes 2 Bytes 2 Byte 4 Bytes + 256B 4 Bytes 4 Bytes 1 Byte 4 Bytes + 256B 4 Bytes 4 Bytes Maximum Frequency 104 MHz 104 MHz 104 MHz 104 MHz 104 MHz 104 MHz 104 MHz 33 MHz 104 MHz 104 MHz 104MHz 100 MHz 100MHz 104MHz 104 MHz 104 MHz 104 MHz 104 MHz 104MHz 104MHz 104 MHz 33 MHz HOLD OPERATION HOLD# is used in conjunction with CE# to select the IS25LQ080. When the devices are selected and a serial sequence is underway, HOLD# can be used to pause the serial communication with the master device without resetting the serial sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume serial communication, HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs to Sl will be ignored while SO is in the high impedance state. Integrated Silicon Solution, Inc.- www.issi.com Rev. A 10/18/2012 11 11 Page

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