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PDF IS25LQ040 Data sheet ( Hoja de datos )
| Número de pieza | IS25LQ040 | |
| Descripción | 4Mbit Single Operating Voltage Serial Flash Memory | |
| Fabricantes | ISSI | |
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4 Mbit Single Operating Voltage Serial Flash Memory With 104
MHz Dual- or 100MHz Quad-Output SPI Bus Interface
IS25LQ040
FEATURES
• Single Power Supply Operation
- Low voltage range: 2.3 V - 3.6 V
• Memory Organization
- IS25LQ040: 512K x 8 (4 Mbit)
• Cost Effective Sector/Block Architecture
- 4Mb : Uniform 4KByte sectors / sixteen uniform
64KByte blocks
• Serial Peripheral Interface (SPI) Compatible
- Supports single-, dual- or quad-output
- Supports SPI Modes 0 and 3
- Maximum 33 MHz clock rate for normal read
- Maximum 104 MHz clock rate for fast read
- Maximum 208MHz clock rate equivalent Dual SPI
- Maximum 400MHz clock rate equivalent Quad SPI
• Byte Program Operation
- Typical 10 us/Byte
• Page Program (up to 256 Bytes) Operation
- Maximum 0.7ms per page program
• Sector, Block or Chip Erase Operation
- Sector Erase (4KB)150ms (Typ)
- Block Erase (64KB)500ms (Typ)
- Chip Erase 1s (4Mb)
• Low Power Consumption
- Max 12 mA active read current
- Max 20 mA program/erase current
- Max 50 uA standby current
• Hardware Write Protection
- Protect and unprotect the device from write
operation by Write Protect (WP#) Pin
• Software Write Protection
- The Block Protect (BP3, BP2, BP1, BP0) bits
allow partial or entire memory to be configured as
read-only
• High Product Endurance
- Guaranteed 100,000 program/erase cycles per
single sector
- Minimum 20 years data retention
• Industrial Standard Pin-out and Package
- 8-pin 208mil SOIC
- 8-pin 150mil SOIC
- 8-pin 150mil VVSOP
- 8-contact WSON
- PDIP
- Lead-free (Pb-free), package
•Additional 256-byte Security information one-time
programmable (OTP) area
•Special protect function
- Safe guard function (Appendix 1)
- Sector unlock function (Appendix 2)
GENERAL DESCRIPTION
The IS25LQ040 is 4 Mbit Serial Peripheral Interface (SPI) Flash memories, providing single-, dual or quad-
output. The devices are designed to support a 33 MHz fclock rate in normal read mode, and 104 MHz in fast
read (Quad output is 100MHz), the fastest in the industry. The devices use a single low voltage power supply,
ranging from 2.3 Volt to 3.6 Volt, to perform read, erase and program operations. The devices can be
programmed in standard EPROM programmers.
The IS25LQ040 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output (Sl), Serial
Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. The devices support page program mode,
where 1 to 256 bytes data can be programmed into the memory in one program operation. These devices are
divided into uniform 4 KByte sectors or uniform 64 KByte blocks.
The IS25LQ040 are offered in 8-pin SOIC 208mil, 8-pin PDIP, 8-pin VVSOP and 8-contact WSON.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
09/13/2012
1
1 page  
SPI MODES DESCRIPTION
IS25LQ040
Multiple IS25LQ040 devices can be connected on the
SPI serial bus and controlled by a SPI Master, i.e.
microcontroller, as shown in Figure 1. The devices
support either of two SPI modes:
Mode 0 (0, 0)
Mode 3 (1, 1)
The difference between these two modes is the clock
polarity when the SPI master is in Stand-by mode: the
serial clock remains at “0” (SCK = 0) for Mode 0 and
the clock remains at “1” (SCK = 1) for Mode 3. Please
refer to Figure 2. For both modes, the input data is
latched on the rising edge of Serial Clock (SCK), and
the output data is available from the falling edge of
SCK.
Figure 1. Connection Diagram among SPI Master and SPI Slaves (Memory Devices)
SPI Interface with
(0,0) or (1,1)
SDI
SDI
SCK
SPI Master
(i.e. Microcontroller)
CS3 CS2 CS1
SCK SO SI
SCK SO SI
SCK SO SI
SPI Memory
Device
CE# WP#
HOLD#
SPI Memory
Device
CE# WP#
HOLD#
SPI Memory
Device
CE# WP#
HOLD#
Note: 1. The Write Protect (WP#) and Hold (HOLD#) signals should be driven high or low as
Figure 2. SPI Modes Supported
SCK
Mode 0 (0,0)
SCK
Mode 3 (1,1)
SI
Input mode
SO
MSb
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
09/13/2012
MSb
5
5 Page 
IS25LQ040
DEVICE OPERATION (CONTINUED)
RDID COMMAND (READ PRODUCT
IDENTIFICATION)/ Release Power-down
OPERATION
shifting the instruction code ‘‘ABh’’ and driving CE#
The Release from Power-down or High performance high as shown in figure 3.
Mode / Device ID instruction is a multi-purpose
Release from power-down will take the time duration of
instruction. The Read Product Identification (RDID)
tRES1 before the device will resume normal operation
instruction is for reading out the old style of 8-bit
and other instructions are accepted. The CE# pin must
Electronic Signature, whose values are shown as table remain high during the tRES1 time duration. If the
of ID Definitions. This is not same as RDID or JEDEC Release from Power-down / RDID instruction is issued
ID instruction. It’s not recommended to use for new
while an Erase, Program or Write cycle is in process
design. For new design, please use RDID or JEDEC ID (when BUSY equals 1) the instruction is ignored and
instruction.
will not have any effects on the current cycle
The RDES instruction code is followed by three dummy
bytes, each bit being latched-in on SI during the rising Table 12. Product Identification
edge of SCK. Then the Device ID is shifted out on SO
with the MSB first, each bit been shifted out during the
falling edge of SCK. The RDES instruction is ended by
CE# goes high. The Device ID outputs repeatedly if
continuously send the additional clock cycles on SCK
Product Identification
First Byte
Manufacturer ID
Second Byte
Data
9Dh
7Fh
while CE# is at low.
Device ID:
Device ID1
Device ID2
To release the device from the power-down state Mode,
the instruction is issued by driving the CE# pin low,
IS25LQ040C
12h
43h
Figure 3. Read Product Identification Sequence
CE#
SCK
SI
01
78 9
31
INSTRUCTION
1010 1011b
3 Dummy Bytes
38 39
46 47
54
HIGH IMPEDANCE
SO
Device ID1
Device ID1
Device ID1
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
09/13/2012
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet IS25LQ040.PDF ] | |
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