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IS25LD010 の電気的特性と機能

IS25LD010のメーカーはISSIです、この部品の機能は「512Kbit / 1Mbit / 2Mbit Single Operating Voltage Serial Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS25LD010
部品説明 512Kbit / 1Mbit / 2Mbit Single Operating Voltage Serial Flash Memory
メーカ ISSI
ロゴ ISSI ロゴ 




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IS25LD010 Datasheet, IS25LD010 PDF,ピン配置, 機能
512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial
Flash Memory With 100 MHz Dual-Output SPI Bus
IS25LD512/010/020
FEATURES
Single Power Supply Operation
- Low voltage range: 2.3 V – 3.6 V
• Memory Organization
- IS25LD512: 64K x 8 (512 Kbit)
- IS25LD010: 128K x 8 (1 Mbit)
- IS25LD020: 256K x 8 (2 Mbit)
Cost Effective Sector/Block Architecture
- 512Kb : Uniform 4KByte sectors / Two uniform
32KByte blocks
- 1Mb : Uniform 4KByte sectors / Four uniform
32KByte blocks
- 2Mb : Uniform 4KByte sectors / Four uniform
64KByte blocks
• Low standby current 1uA (Typ)
Serial Peripheral Interface (SPI) Compatible
- Supports single- or dual-output
- Supports SPI Modes 0 and 3
- Maximum 33 MHz clock rate for normal read
- Maximum 100 MHz clock rate for fast read
Page Program (up to 256 Bytes) Operation
- Typical 2 ms per page program
Sector, Block or Chip Erase Operation
- Maximum 10 ms sector, block or chip erase
Low Power Consumption
- Typical 10 mA active read current
- Typical 15 mA program/erase current
Hardware Write Protection
- Protect and unprotect the device from write
operation by Write Protect (WP#) Pin
Software Write Protection
- The Block Protect (BP2, BP1, BP0) bits allow
partial or entire memory to be configured as read-
only
High Product Endurance
- Guaranteed 200,000 program/erase cycles per
single sector
- Minimum 20 years data retention
Industrial Standard Pin-out and Package
- 8-pin 150mil SOIC
- 8-pin VVSOP
- 8-contact WSON
- 8-pin TSSOP
- 8-pin USON
- Lead-free (Pb-free) package
Security function
- Build in Safe Guard function and sector unlock
function to make the flash Robust (Appendix1&2)
GENERAL DESCRIPTION
The IS25LD512/010/020 are 512Kbit/ 1Mbit / 2Mbit Serial Peripheral Interface (SPI) Flash memories, providing
single- or dual-output. The devices are designed to support a 33 MHz clock rate in normal read mode, and 100
MHz in fast read, the fastest in the industry. The devices use a single low voltage power supply, wide operating
voltage ranging from 2.3 Volt to 3.6 Volt, to perform read, erase and program operations. The devices can be
programmed in standard EPROM programmers.
The IS25LD512/010/020 are accessed through a 4-wire SPI Interface consisting of Serial Data Input/Output
(SlO), Serial Data Output (SO), Serial Clock (SCK), and Chip Enable (CE#) pins. They comply with all
recognized command codes and operations. The dual-output fast read operation provides and effective serial
data rate of 200MHz.
The devices support page program mode, where 1 to 256 bytes data can be programmed into the memory in
one program operation. These devices are divided into uniform 4 KByte sectors or uniform 32 KByte
blocks.(IS25LD020 is uniform 4 KByte sectors or uniform 64 KByte).
The IS25LD512/010/020 are manufactured on pFLASH™’s advanced non-volatile technology. The devices are
offered in 8-pin SOIC 150mil, 8-contact WSON, 8-pin VVSOP, 8-pin USON and 8-pin TSSOP. The devices
operate at wide temperatures between -40°C to +105°C.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
08/09/2012
1

1 Page





IS25LD010 pdf, ピン配列
BLOCK DIAGRAM
IS25LD512/010/020
SIO
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
08/09/2012
3


3Pages


IS25LD010 電子部品, 半導体
REGISTERS (CONTINUED)
STATUS REGISTER
IS25LD512/010/020
Refer to Tables 5 and 6 for Status Register Format and are allowed. The WEL bit is set by a Write Enable
Status Register Bit Definitions.
(WREN) instruction. Each write register, program and
erase instruction must be preceded by a WREN
The BP0, BP1, BP2, and SRWD are volatile memory instruction. The WEL bit can be reset by a Write
cells that can be written by a Write Status Register
Disable (WRDI) instruction. It will automatically be the
(WRSR) instruction. The default value of the BP2, BP1, reset after the completion of a write instruction.
BP0 were set to “0” and SRWD bits was set to “0” at
factory. Once a “0” or “1”is written, it will not be
BP2, BP1, BP0 bits: The Block Protection (BP2, BP1,
changed by device power-up or power-down, and can BP0) bits are used to define the portion of the memory
only be altered by the next WRSR instruction. The
area to be protected. Refer to Tables 7, 8 and 9 for the
Status Register can be read by the Read Status
Block Write Protection bit settings. When a defined
Register (RDSR). Refer to Table 10 for Instruction Set. combination of BP2, BP1 and BP0 bits are set, the
corresponding memory area is protected. Any program
The function of Status Register bits are described as or erase operation to that area will be inhibited. Note:
follows:
a Chip Erase (CHIP_ER) instruction is executed
successfully only if all the Block Protection Bits are set
WIP bit: The Write In Progress (WIP) bit is read-only, as “0”s.
and can be used to detect the progress or completion
of a program or erase operation. When the WIP bit is SRWD bit: The Status Register Write Disable (SRWD)
“0”, the device is ready for a write status register,
bit operates in conjunction with the Write Protection
program or erase operation. When the WIP bit is “1”, (WP#) signal to provide a Hardware Protection Mode.
the device is busy.
When the SRWD is set to “0”, the Status Register is
not write-protected. When the SRWD is set to “1” and
WEL bit: The Write Enable Latch (WEL) bit indicates the WP# is pulled low (VIL), the volatile bits of Status
the status of the internal write enable latch. When the Register (SRWD, BP2, BP1, BP0) become read-only,
WEL is “0”, the write enable latch is disabled, and all and a WRSR instruction will be ignored. If the SRWD is
write operations, including write status register, page set to “1” and WP# is pulled high (VIH), the Status
program, sector erase, block and chip erase operations Register can be changed by a WRSR instruction.
are inhibited. When the WEL bit is “1”, write operations
Table 5. Status Register Format
Default (flash bit)
Bit 7
SRWD1
0
Bit 6 Bit 5
Reserved
0
Bit 4
BP2
0
Bit 3
BP1
0
Bit 2
BP0
0
Bit 1
WEL
0
Bit 0
WIP
0
Integrated Silicon Solution, Inc.- www.issi.com
Rev. A
08/09/2012
6

6 Page



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部品番号部品説明メーカ
IS25LD010

512Kbit / 1Mbit / 2Mbit Single Operating Voltage Serial Flash Memory

ISSI
ISSI


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