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PDF 24AA128 Data sheet ( 特性 )

部品番号 24AA128
部品説明 128K I2C CMOS Serial EEPROM
メーカ MicrochipTechnology
ロゴ MicrochipTechnology ロゴ 

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24AA128 Datasheet, 24AA128 PDF,ピン配置, 機能
24AA128/24LC128/24FC128
128K I2CCMOS Serial EEPROM
Device Selection Table
Part
Number
VCC
Range
Max. Clock
Frequency
Temp.
Ranges
• Temperature Ranges:
- Industrial (I):
-40C to +85C
- Automotive (E): -40C to +125C
24AA128 1.7-5.5V 400 kHz(1)
24LC128
24FC128
2.5-5.5V
1.7-5.5V
400 kHz
1 MHz(2)
Note 1: 100 kHz for VCC < 2.5V.
2: 400 kHz for VCC < 2.5V.
I
I, E
I
Features:
• Single Supply with Operation down to 1.7V for
24AA128/24FC128 devices, 2.5V for 24LC128
Devices
• Low-Power CMOS Technology:
- Write current 3 mA, typical
- Standby current 100 nA, typical
• 2-Wire Serial Interface, I2C™ Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• 1 MHz Clock for FC Versions
• Page Write Time 5 ms, typical
• Self-Timed Erase/Write Cycle
• 64-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4000V
• More than 1 Million Erase/Write Cycles
• Data Retention > 200 years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN, MSOP, and Chip Scale Packages
• Pb-Free and RoHS Compliant
Description:
The Microchip Technology Inc. 24AA128/24LC128/
24FC128 (24XX128*) is a 16K x 8 (128 Kbit) Serial
Electrically Erasable PROM (EEPROM), capable of
operation across a broad voltage range (1.7V to 5.5V).
It has been developed for advanced, low-power
applications such as personal communications or data
acquisition. This device also has a page write capabil-
ity of up to 64 bytes of data. This device is capable of
both random and sequential reads up to the 128K
boundary. Functional address lines allow up to eight
devices on the same bus, for up to 1 Mbit address
space. This device is available in the standard 8-pin
plastic DIP, SOIC (3.90 mm and 5.28 mm), TSSOP,
MSOP, DFN, TDFN and Chip Scale packages.
Block Diagram
A0 A1 A2 WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
I/O SCL
SDA
XDEC
EEPROM
Array
Page Latches
YDEC
VCC
VSS Sense Amp.
R/W Control
*24XX128 is used in this document as a generic part number
for the 24AA128/24LC128/24FC128 devices.
Package Types
PDIP/SOIC
TSSOP/MSOP1
DFN/TDFN
CS (Chip Scale)2
A0 1
A1 2
A2 3
VSS 4
8 VCC
A0
7 WP
A1
6 SCL
A2
5 SDA VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
Note 1: Pins A0 and A1 are no-connects for the MSOP package only.
2: Available in I-temp, “AA” only.
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
WP
VCC A1 A0
123
45
6 78
SDA SCL VSS
(TOP DOWN VIEW,
BALLS NOT VISIBLE)
A2
2010 Microchip Technology Inc.
DS21191S-page 1

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