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24AA128 の電気的特性と機能

24AA128のメーカーはMicrochipTechnologyです、この部品の機能は「128K I2C CMOS Serial EEPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 24AA128
部品説明 128K I2C CMOS Serial EEPROM
メーカ MicrochipTechnology
ロゴ MicrochipTechnology ロゴ 




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24AA128 Datasheet, 24AA128 PDF,ピン配置, 機能
24AA128/24LC128/24FC128
128K I2CCMOS Serial EEPROM
Device Selection Table
Part
Number
VCC
Range
Max. Clock
Frequency
Temp.
Ranges
• Temperature Ranges:
- Industrial (I):
-40C to +85C
- Automotive (E): -40C to +125C
24AA128 1.7-5.5V 400 kHz(1)
24LC128
24FC128
2.5-5.5V
1.7-5.5V
400 kHz
1 MHz(2)
Note 1: 100 kHz for VCC < 2.5V.
2: 400 kHz for VCC < 2.5V.
I
I, E
I
Features:
• Single Supply with Operation down to 1.7V for
24AA128/24FC128 devices, 2.5V for 24LC128
Devices
• Low-Power CMOS Technology:
- Write current 3 mA, typical
- Standby current 100 nA, typical
• 2-Wire Serial Interface, I2C™ Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• 1 MHz Clock for FC Versions
• Page Write Time 5 ms, typical
• Self-Timed Erase/Write Cycle
• 64-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4000V
• More than 1 Million Erase/Write Cycles
• Data Retention > 200 years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN, MSOP, and Chip Scale Packages
• Pb-Free and RoHS Compliant
Description:
The Microchip Technology Inc. 24AA128/24LC128/
24FC128 (24XX128*) is a 16K x 8 (128 Kbit) Serial
Electrically Erasable PROM (EEPROM), capable of
operation across a broad voltage range (1.7V to 5.5V).
It has been developed for advanced, low-power
applications such as personal communications or data
acquisition. This device also has a page write capabil-
ity of up to 64 bytes of data. This device is capable of
both random and sequential reads up to the 128K
boundary. Functional address lines allow up to eight
devices on the same bus, for up to 1 Mbit address
space. This device is available in the standard 8-pin
plastic DIP, SOIC (3.90 mm and 5.28 mm), TSSOP,
MSOP, DFN, TDFN and Chip Scale packages.
Block Diagram
A0 A1 A2 WP
HV Generator
I/O
Control
Logic
Memory
Control
Logic
I/O SCL
SDA
XDEC
EEPROM
Array
Page Latches
YDEC
VCC
VSS Sense Amp.
R/W Control
*24XX128 is used in this document as a generic part number
for the 24AA128/24LC128/24FC128 devices.
Package Types
PDIP/SOIC
TSSOP/MSOP1
DFN/TDFN
CS (Chip Scale)2
A0 1
A1 2
A2 3
VSS 4
8 VCC
A0
7 WP
A1
6 SCL
A2
5 SDA VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
Note 1: Pins A0 and A1 are no-connects for the MSOP package only.
2: Available in I-temp, “AA” only.
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
WP
VCC A1 A0
123
45
6 78
SDA SCL VSS
(TOP DOWN VIEW,
BALLS NOT VISIBLE)
A2
2010 Microchip Technology Inc.
DS21191S-page 1

1 Page





24AA128 pdf, ピン配列
24AA128/24LC128/24FC128
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): VCC = +2.5V to 5.5V TA = -40°C to 125°C
Param.
No.
Sym.
Characteristic
Min.
Max. Units
Conditions
1 FCLK Clock frequency
— 100 kHz 1.7V VCC 2.5V
— 400
2.5V VCC 5.5V
— 400
1.7V VCC 2.5V 24FC128
— 1000
2.5V VCC 5.5V 24FC128
2 THIGH Clock high time
4000 — ns 1.7V VCC 2.5V
600 —
2.5V VCC 5.5V
600 —
1.7V VCC 2.5V 24FC128
500 —
2.5V VCC 5.5V 24FC128
3 TLOW Clock low time
4700 — ns 1.7V VCC 2.5V
1300
2.5V VCC 5.5V
1300
1.7V VCC 2.5V 24FC128
500 —
2.5V VCC 5.5V 24FC128
4 TR SDA and SCL rise time
(Note 1)
1000
ns 1.7V VCC 2.5V
— 300
2.5V VCC 5.5V
— 300
1.7V VCC 5.5V 24FC128
5 TF SDA and SCL fall time
(Note 1)
— 300 ns All except, 24FC128
— 100
1.7V VCC 5.5V 24FC128
6 THD:STA Start condition hold time 4000 — ns 1.7V VCC 2.5V
600 —
2.5V VCC 5.5V
600 —
1.7V VCC 2.5V 24FC128
250 —
2.5V VCC 5.5V 24FC128
7 TSU:STA Start condition setup time 4700 — ns 1.7V VCC 2.5V
600 —
2.5V VCC 5.5V
600 —
1.7V VCC 2.5V 24FC128
250 —
2.5V VCC 5.5V 24FC128
8 THD:DAT Data input hold time
0 — ns (Note 2)
9 TSU:DAT Data input setup time
250 — ns 1.7V VCC 2.5V
100 —
2.5V VCC 5.5V
100 —
1.7V VCC 5.5V 24FC128
10 TSU:STO Stop condition setup time
4000
ns 1.7 V VCC 2.5V
600 —
2.5 V VCC 5.5V
600 —
1.7V VCC 2.5V 24FC128
250 —
2.5 V VCC 5.5V 24FC128
11 TSU:WP WP setup time
4000 — ns 1.7V VCC 2.5V
600 —
2.5V VCC 5.5V
600 —
1.7V VCC 5.5V 24FC128
12 THD:WP WP hold time
4700 — ns 1.7V VCC 2.5V
1300
2.5V VCC 5.5V
1300
1.7V VCC 5.5V 24FC128
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site
at www.microchip.com.
2010 Microchip Technology Inc.
DS21191S-page 3


3Pages


24AA128 電子部品, 半導体
24AA128/24LC128/24FC128
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line, while the clock
(SCL) is high, determines a Stop condition. All
operations must end with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse, which is associated with this Acknowledge
bit.
Note:
The 24XX128 does not generate any
Acknowledge bits if an internal
programming cycle is in progress.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX128) will leave the data line high to enable
the master to generate the Stop condition.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A) (B) (D) (D)
SCL
(C) (A)
SDA
Start
Condition
Address or
Acknowledge
Valid
FIGURE 4-2:
ACKNOWLEDGE TIMING
Data
Allowed
to Change
Acknowledge
Bit
SCL 1 2 3 4 5 6 7 8 9 1 2 3
Stop
Condition
SDA
Data from transmitter
Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Data from transmitter
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
DS21191S-page 6
2010 Microchip Technology Inc.

6 Page



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部品番号部品説明メーカ
24AA128

128K I2C CMOS Serial EEPROM

MicrochipTechnology
MicrochipTechnology


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