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24AA08 の電気的特性と機能

24AA08のメーカーはMicrochipTechnologyです、この部品の機能は「8K I2C Serial EEPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 24AA08
部品説明 8K I2C Serial EEPROM
メーカ MicrochipTechnology
ロゴ MicrochipTechnology ロゴ 




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24AA08 Datasheet, 24AA08 PDF,ピン配置, 機能
24AA08/24LC08B
8K I2CSerial EEPROM
Device Selection Table
Part
Number
VCC
Range
Max. Clock
Frequency
24AA08
1.7-5.5
400 kHz(1)
24LC08B 2.5-5.5
400 kHz
Note 1: 100 kHz for VCC <2.5V
Temp.
Ranges
I
I, E
Features:
• Single Supply with Operation down to 1.7V for
24AA08 Devices, 2.5V for 24LC08B Devices
• Low-Power CMOS Technology:
- Read current 1 mA, max.
- Standby current 1 μA, max
• 2-Wire Serial Interface, I2C™ Compatible
• Schmitt Trigger inputs for Noise Suppression
• Output Slope Control to eliminate Ground Bounce
• 100 kHz and 400 kHz Clock Compatibility
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• Hardware Write-Protect
• ESD Protection >4,000V
• More than 1 Million Erase/Write Cycles
• Data Retention >200 years
• Factory Programming Available
• Packages include 8-lead PDIP, SOIC, TSSOP,
DFN, TDFN, MSOP and 5-lead SOT-23
• Pb-Free and RoHS Compliant
• Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
*24XX08 is used in this document as a generic part
number for the 24AA08/24LC08B devices.
Description:
The Microchip Technology Inc. 24AA08/24LC08B
(24XX08*) is a 8 Kbit Electrically Erasable PROM. The
device is organized as four blocks of 256 x 8-bit
memory with a 2-wire serial interface. Low-voltage
design permits operation down to 1.7V, with standby
and active currents of only 1 μA and 1 mA,
respectively. The 24XX08 also has a page write
capability for up to 16 bytes of data. The 24XX08 is
available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, 2x3 DFN, 2x3 TDFN and MSOP
packages, and is also available in the 5-lead SOT-23
package. All packages are Pb-free and RoHS
compliant.
Block Diagram
HV
WP Generator
I/O
Control
Logic
I/O
SCL
SDA
VCC
VSS
Memory
Control
Logic
XDEC
EEPROM
Array
Page
Latches
YDEC
Sense Amp.
R/W Control
Package Types
PDIP, MSOP
SOIC, TSSOP
A0 1
A1 2
A2 3
VSS 4
8 VCC A0
7 WP A1
6 SCL A2
5 SDA VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SOT-23-5
DFN/TDFN
SCL 1
Vss
SDA
2
3
5 WP
4 Vcc
A0 1
A1 2
A2 3
VSS 4
8 VCC
7 WP
6 SCL
5 SDA
Note:
Pins A0, A1 and A2 are not used by the 24XX08. (No
internal connections).
© 2009 Microchip Technology Inc.
DS21710J-page 1

1 Page





24AA08 pdf, ピン配列
24AA08/24LC08B
TABLE 1-2: AC CHARACTERISTICS
AC CHARACTERISTICS
VCC = +1.7V to +5.5V
Industrial (I):
TA = -40°C to +85°C
Automotive (E): TA = -40°C to +125°C
Param.
No.
Symbol
Characteristic
Min.
Typ. Max. Units
Conditions
1
FCLK
Clock frequency
— — 400 kHz 2.5V VCC 5.5V
— — 100
1.7V VCC < 2.5V (24AA08)
2 THIGH Clock high time
600 — — ns 2.5V VCC 5.5V
4000 — —
1.7V VCC < 2.5V (24AA08)
3 TLOW Clock low time
1300 — — ns 2.5V VCC 5.5V
4700 — —
1.7V VCC < 2.5V (24AA08)
4 TR
SDA and SCL rise time
(Note 1)
— 300 ns 2.5V VCC 5.5V
— 1000
1.7V VCC < 2.5V (24AA08)
5 TF SDA and SCL fall time — — 300 ns (Note 1)
6
THD:STA Start condition hold time
600
— — ns 2.5V VCC 5.5V
4000 — —
1.7V VCC < 2.5V (24AA08)
7 TSU:STA Start condition setup
time
600 — — ns 2.5V VCC 5.5V
4700 — —
1.7V VCC < 2.5V (24AA08)
8 THD:DAT Data input hold time
0 — — ns (Note 2)
9 TSU:DAT Data input setup time
100 — — ns 2.5V VCC 5.5V
250 — —
1.7V VCC < 2.5V (24AA08)
10 TSU:STO Stop condition setup
time
600 — — ns 2.5V VCC 5.5V
4000 — —
1.7V VCC < 2.5V (24AA08)
11 TAA
Output valid from clock
(Note 2)
— 900 ns 2.5V VCC 5.5V
— 3500
1.7V VCC < 2.5V (24AA08)
12
TBUF
Bus free time: Time the
1300
— ns 2.5V VCC 5.5V
bus must be free before 4700 — —
1.7V VCC < 2.5V (24AA08)
a new transmission can
start
13 TOF
Output fall time from VIH
minimum to VIL
maximum
— 250 ns 2.5V VCC 5.5V
— 250
1.7V VCC < 2.5V (24AA08)
14 TSP
Input filter spike
suppression
(SDA and SCL pins)
— — 50 ns (Notes 1 and 3)
15 TWC Write cycle time (byte or —
page)
— 5 ms —
16 —
Endurance
1M — — cycles 25°C, (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
© 2009 Microchip Technology Inc.
DS21710J-page 3


3Pages


24AA08 電子部品, 半導体
24AA08/24LC08B
3.0 FUNCTIONAL DESCRIPTION
The 24XX08 supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX08 works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus Not Busy (A)
Both data and clock lines remain high.
4.2 Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3 Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first-in first-
out (FIFO) fashion.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
Note:
The 24XX08 does not generate any
Acknowledge bits if an internal program-
ming cycle is in progress.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XX08) will leave the data line
high to enable the master to generate the Stop
condition.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
SCL
(B)
(D)
(D)
(C) (A)
SDA
Start
Condition
Address or
Data
Acknowledge Allowed
Valid
to Change
Stop
Condition
DS21710J-page 6
© 2009 Microchip Technology Inc.

6 Page



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