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22C10 の電気的特性と機能

22C10のメーカーはCatalystSemiconductorです、この部品の機能は「256-BitNonvolatileCMOSStaticRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 22C10
部品説明 256-BitNonvolatileCMOSStaticRAM
メーカ CatalystSemiconductor
ロゴ CatalystSemiconductor ロゴ 




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22C10 Datasheet, 22C10 PDF,ピン配置, 機能
CAT22C10
256-Bit Nonvolatile CMOS Static RAM
FEATURES
s Single 5V Supply
s Fast RAM Access Times:
–200ns
–300ns
s Infinite E2PROM to RAM Recall
s CMOS and TTL Compatible I/O
s Power Up/Down Protection
s 100,000 Program/Erase Cycles (E2PROM)
s Low CMOS Power Consumption:
–Active: 40mA Max.
–Standby: 30 µA Max.
s JEDEC Standard Pinouts:
–18-pin DIP
–16-pin SOIC
s 10 Year Data Retention
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT22C10 NVRAM is a 256-bit nonvolatile memory
organized as 64 words x 4 bits. The high speed Static
RAM array is bit for bit backed up by a nonvolatile
E2PROM array which allows for easy transfer of data
from RAM array to E2PROM (STORE) and from
E2PROM to RAM (RECALL). STORE operations are
completed in 10ms max. and RECALL operations typi-
cally within 1.5µs. The CAT22C10 features unlimited
RAM write operations either through external RAM
writes or internal recalls from E2PROM. Internal false
store protection circuitry prohibits STORE operations
when VCC is less than 3.0V.
The CAT22C10 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles (E2PROM)
and has a data retention of 10 years. The device is
available in JEDEC approved 18-pin plastic DIP and 16-
pin SOIC packages.
PIN CONFIGURATION
DIP Package (P)
SOIC Package (J)
NC
A4
A3
A2
A1
A0
CS
Vss
STORE
1
2
3
4
5
6
7
8
9
1 8 Vcc
1 7 NC
1 6 A5
1 5 I/O3
1 4 I/O2
13 I/O1
12 I/O0
11 WE
A4
A3
A2
A1
A0
CS
Vss
STORE
1
2
3
4
5
6
7
8
10 RECALL
22C10 F01
1 6 Vcc
1 5 A5
1 4 I/O4
13 I/O3
12 I/O2
11 I/O1
10 WE
9 RECALL
22C10 F02
PIN FUNCTIONS
Pin Name
A0–A5
I/O0–I/O3
WE
CS
RECALL
STORE
VCC
VSS
NC
Function
Address
Data In/Out
Write Enable
Chip Select
Recall
Store
+5V
Ground
No Connect
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25018-0A 2/98 N-1

1 Page





22C10 pdf, ピン配列
CAT22C10
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(2) .............. -2.0 to +VCC +2.0V
VCC with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
NEND(1)
TDR(1)
VZAP(1)
ILTH(1)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
100,000
10
2000
100
Max.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
D.C. OPERATING CHARACTERISTICS
VCC = +5V ±10%, unless otherwise specified.
Symbol
ICC
Parameter
Current Consumption
(Operating)
Min.
Limits
Typ.
Max.
40
ISB Current Consumption
(Standby)
ILI Input Current
ILO Output Leakage Current
VIH High Level Input Voltage
VIL Low Level Input Voltage
VOH High Level Output Voltage
VOL Low Level Output Voltage
VDH RAM Data Holding Voltage
2
0
2.4
1.5
30
10
10
VCC
0.8
0.4
5.5
Unit
mA
µA
µA
µA
V
V
V
V
V
Conditions
All Inputs = 5.5V
TA = 0°C
All I/O’s Open
CS = VCC
All I/O’s Open
0 VIN 5.5V
0 VOUT 5.5V
IOH = –2mA
IOL = 4.2mA
VCC
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Parameter
Max.
Unit
Conditions
CI/O(1)
CIN(1)
Input/Output Capacitance
Input Capacitance
10 pF
6 pF
VI/O = 0V
VIN = 0V
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V.
3 Doc. No. 25018-0A 2/98 N-1


3Pages


22C10 電子部品, 半導体
CAT22C10
DEVICE OPERATION
The configuration of the CAT22C10 allows a common
address bus to be directly connected to the address
inputs. Additionally, the Input/Output (I/O) pins can be
directly connected to a common I/O bus if the bus has
less than 1 TTL load and 100pF capacitance. If not, the
I/O path should be buffered.
When the chip select (CS) pin goes low, the device is
activated. When CS is forced high, the device goes into
the standby mode and consumes very little current. With
the nonvolatile functions inhibited, the device operates
like a Static RAM. The Write Enable (WE) pin selects a
write operation when WE is low and a read operation
when WE is high. In either of these modes, an array byte
(4 bits) can be addressed uniquely by using the address
lines (A0–A5), and that byte will be read or written to
through the Input/Output pins (I/O0–I/O3).
The nonvolatile functions are inhibited by holding the
STORE input and the RECALL input high. When the
RECALL input is taken low, it initiates a recall operation
which transfers the contents of the entire E2PROM array
into the Static RAM. When the STORE input is taken low,
it initiates a store operation which transfers the entire
Static RAM array contents into the E2PROM array.
Standby Mode
The chip select (CS) input controls all of the functions of
the CAT22C10. When a high level is supplied to the CS
pin, the device goes into the standby mode where the
outputs are put into a high impendance state and the
power consumption is drastically reduced. With ISB less
than 100µA in standby mode, the designer has the
flexibility to use this part in battery operated systems.
Read
When the chip is enabled (CS = low), the nonvolatile
functions are inhibited (STORE = high and RECALL =
high). With the Write Enable (WE) pin held high, the data
in the Static RAM array may be accessed by selecting an
address with input pins A0–A5. This will occur when the
outputs are connected to a bus which is loaded by no
more than 100pF and 1 TTL gate. If the loading is greater
than this, some additional buffering circuitry is recom-
mended.
Figure 1. Read Cycle Timing
ADDRESS
CS
DATA I/O
tRC
tAA
tLZ
tCO
tOH
DATA VALID
tHZ
HIGH-Z
5153 FHD F06
Doc. No. 25018-0A 2/98 N-1
6

6 Page



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部品番号部品説明メーカ
22C10

256-BitNonvolatileCMOSStaticRAM

CatalystSemiconductor
CatalystSemiconductor


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