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PDF AK8186B Data sheet ( Hoja de datos )
| Número de pieza | AK8186B | |
| Descripción | Multi Output Clock Generator | |
| Fabricantes | AKM | |
| Logotipo |  |
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Preliminary
AK8186B
Multi Output Clock Generator with
Integrated 2.0GHz VCO
AK8186B
FEATURES
Low phase noise PLL : RMS Jitter < 300fs
On-chip VCO tunes from 1.75GHz to 2.25GHz
External VCO/VCXO to 500MHz optional
1 differential or 2 single-ended Inputs
Reference Switchover/Holdover modes
Lock Detect
3 pairs of 1GHz LVPECL outputs
2 pairs of 800MHz LVDS outputs
8 250MHz CMOS outputs (two per LVDS)
Serial control register interface
3.3V+/-5% Operating Voltage
2.5V-3.3V LVPECL Drive Voltage
Operating Temperature: -40 to +85°C
Package: 64-pin Leadless QFN (Pb free)
Pin compatible with AD9516-3
DESCRIPTION
The AK8186B is a multi-output clock generator with
sub-ps jitter performance. The on-chip VCO tunes
from 1.75GHz to 2.25GHz.
The distribution section has three pairs of LVPECL
buffers (6 outputs) and two pairs of LVDS buffers (4
outputs)/eight CMOS buffers (two per LVDS
outputs). The LVPECL outputs operate up to
1GHz, the LVDS outputs operate up to 800MHz
and the CMOS outputs operate up to 250MHz.
Each pair of the outputs has a divider. The
LVPECL outputs have the division range of 1 to 32.
The LVDS and CMOS outputs have the 1 to 1024.
The AK8186B operates at 3.3V and the LVPECL
outputs are supplied independently from 2.375V to
3.6V. The operating temperature range is from -40
to +85°C. The part is available in a 9mm 9 mm
64-pin Leadless-QFN (Pb free) package.
ORDERING INFORMATION
Part Number
AK8186B
Marking
AK8186B
Shipping
Packaging
Tape and Reel
Package
64-pin
Leadless QFN
Temperature
Range
-40 to 85 ℃
draft-E-02
-1-
Sep-2012
http://www.Datasheet4U.com
1 page  
PIN FUNCTION
AK8186B
Pin
No.
Pin Name
1 VDD
2 REFMON
3 LD
4 VCP
5 CP
6 STATUS
7 REF_SEL
8, SYNC
9 LF
10 BYPASS
11 VDD
12 VDD
13 CLK
14 CLK
15 NC
16 SCLK
17 CS
18 NC
19 NC
20 NC
21 SDO
22 SDIO
23 RESET
24 PD
25 OUT4
26 OUT4
27 VDD_LVPECL
28 OUT5
29 OUT5
30 VDD
31 VDD
32 VDD
(Continued on next page)
Pin
Type
PWR
OUT
OUT
---
OUT
OUT
IN
IN
IN
---
PWR
PWR
---
---
--
IN
IN
---
---
--
OUT
IN/OUT
IN
IN
OUT
OUT
PWR
OUT
OUT
PWR
PWR
PWR
Description
3.3V Power Supply.
Reference Monitor.
Lock Detect.
3.3V Power Supply for Charge Pump (CP)
Charge Pump Output. Connect to external loop filter.
Status Indication.
Reference Select. L: REF1 H: REF2.
Pulled down with 30k internal resistor.
Manual Synchronization and Manual Holdover.
Active Low. Pulled up with 30 k internal resistor.
Loop Filter Input.
This pin is for bypassing the LDO to ground.
3.3V Power supply.
3.3V Power supply.
Differential Input for the external VCO/VCXO
Differential Input for the external VCO/VCXO
No Connect. Leave open or connected to GND.
Serial clock for the Serial control port.
Pulled down with 30k internal resistor.
Chip Select for the Serial control port.
Active low. Pulled up to VDD with 30 k internal resistor.
No Connect. Leave open or connected to GND.
No Connect. Leave open or connected to GND.
No Connect. Leave open or connected to GND.
Unidirectional Serial Data Out for Serial Control Port.
Bidirectional Serial Data In/Out for Serial Control Port.
Reset.
Active low. Pulled up with 30 k internal resistor.
Power Down.
Active low. Pulled up with 30 k internal resistor.
LVPECL Output 4
LVPECL Output 4
2.5V to 3.3V Power Supply for LVPECL Output (OUT4/OUT4,
OUT5/OUT5).
LVPECL Output 5
LVPECL Output 5
3.3V Power supply
3.3V Power supply.
3.3V Power supply for OUT8/OUT8 and OUT9/OUT9.
draft-E-02
Sep-2012
-5-
5 Page 
AK8186B
Timing Characteristics
Table 7. All specifications at VDD=3.3V5%, VDD_LVPECL= 2.375V to VDD, Ta: -40 to +85℃, unless otherwise noted
Parameter
Symbol
Conditions
MIN TYP MAX
LVPECL Output
Rise/Fall time
Propagation Delay,
CLK-to-LVPECL Ouput
Variation with Temperature
Output Skew *1
Output Duty
LVDS Output
Rise/Fall time
Propagation Delay,
CLK-to-LVPECL Ouput
Variation with Temperature
Output Skew *1
Output Duty
Termination =
50Ω to VDD-LVPECL-2V
0xFn[3:2] = 10 (n=0 to 5)
20% to 80% / 80% to 20%
Same Divider
Different Dividers
750MHz ≤ Fout
500M ≤ Fout < 750MHz
250M ≤ Fout < 500MHz *2
Fout < 250MHz *2 *3
Fout<1000MHz, VDD_LVPECL=3.3V5%
Termination = 100Ω @3.5mA
0x14n[2:1] = 01 (n=0 to 3)
20% to 80% / 80% to 20%
For All Device Values
Same Divider
Different Dividers
*2 *3
30
35
40
45
45
45
175
TBD
TBD
5
13
50
50
50
50
50
225
40
40
70
65
60
55
55
190
TBD
TBD
6
25
50
350
62
150
55
CMOS Output
20% to 80% / 80% to 20%
Rise/Fall time
Cload = 10pF
400 1000
Propagation Delay,
CLK-to-LVPECL Ouput
Variation with Temperature
Output Skew *1
For All Device Values
Same Divider
Different Dividers
TBD
TBD
4
28
66
180
Output Duty
*2 *3
45 50 55
*1) Skew: The Difference between any two similar delay paths while operating at the same voltage and temperature.
_______
*2) Differential input through CLK/CLK pins: Clock input is assumed to be 50% duty.
*3) Single-end input through CLK pin: Clock input is assumed to be 50% duty and Fout < 150 MHz.
Unit
ps
ns
ps/C
ps
ps
%
%
%
%
%
ps
ns
ps/C
ps
ps
%
ps
ns
ps/C
ps
ps
%
draft-E-02
- 11 -
Sep-2012
11 Page | ||
| Páginas | Total 69 Páginas | |
| PDF Descargar | [ Datasheet AK8186B.PDF ] | |
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