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PDF AK8141 Data sheet ( Hoja de datos )
| Número de pieza | AK8141 | |
| Descripción | Register Programable Single Clock Generator | |
| Fabricantes | AKM | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AK8141 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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ASAHI KASEI EMD CORPORATION
Register Programmable
Clock Generator
AK8141
Features
· Input Frequency:
48MHz/24MHz/12MHz/27MHz (Selectable)
· Output Frequency:
27MHz – 50MHz by 1MHz step,
33.75MHz/40.5MHz/49.5MHz (Selectable)
· Low Jitter Performance:
15 ps (Typ.) Period 1s
· Low Current Consumption:
3.5mA (Typ.) at 27MHz, 3.0V
4.5mA (Typ.) at 50MHz, 3.0V
· Output Load:
15pF(Max)
· Supply Voltage:
2.7 – 3.6V
· Operating Temperature Range:
-20 to +85℃
· Package:
8-pin USON
Description
The AK8141 is a single clock generator IC with an
integrated PLL. It can generate a 27.0MHz –
50.0MHz by 1MHz step or 33.75MHz, 40.5MHz,
49.5MHz clock from a 48MHz, 24MHz, 12MHz and
27MHz master clock input frequency. The output can
be enabled or disabled with pin and the frequency
can be changed via three-line serial interface. The
high performance PLL locks to the master clock
input, generating a low jitter, highly accurate clock
output without an external crystal.
Applications
· Digital Still Camera
· Digital Video Camera
Block Diagram
VDD
VSS
CLKIN
OE
INPUT
Buffer
PLL
OUTPUT
Buffer
CLKOUT
Register
XLAT SCLK SDATA
AK8141 Register Programmable Clock Generator
MS0607-E-00
1
May-08
http://www.Datasheet4U.com
1 page  
The brand name
of AKEMD’s IC’s
Serial Interface
SDATA
SCLK
t3 t4
D0
t1 t2
D1
XLAT
A6 A7
t5 t6
t7
Note) It might cause a write access if SCLK rise while XLAT stay at “Low”.
AK8141
Symbol
t1,t2
t3
t4
t5
t6
t7
Parameter
SCLK pulse width
SDATA setup time
SDATA hold time
SCLK rising edge to XLAT falling edge
XLAT pulse width
XLAT rising edge to SCLK falling edge
Min Typ Max Unit
50 ns
50 ns
50 ns
50 ns
50 ns
50 ns
MS0607-E-00
-5-
May-08
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet AK8141.PDF ] | |
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