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PDF AK4482 Data sheet ( Hoja de datos )
| Número de pieza | AK4482 | |
| Descripción | 111dB 192kHz 24-Bit 2ch DS DAC | |
| Fabricantes | AKM | |
| Logotipo |  |
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[AK4482]
AK4482
111dB 192kHz 24-Bit 2ch ΔΣ DAC
GENERAL DESCRIPTION
The AK4482 is a cost-effective 24-bit DAC for digital audio equipments. The modulator uses AKM's
multi-bit architecture, delivering wide dynamic range. The AK4482 has fully differential switched-cap filter
outputs, removing the need for AC coupling capacitors and increasing performance for systems with
excessive clock jitter. The AK4482 support up to 216kHz sampling rate, ideal for BD and AC-3 amplifier
systems. It is housed in a space saving 16pin TSSOP package.
FEATURES
Sampling Rate: 8kHz ∼ 216kHz
128 x Over Sampling (Normal Speed Mode)
64 x Over Sampling (Double Speed Mode)
32 x Over Sampling (Quad Speed Mode)
24 Bit 8 x FIR Digital Filter
- High Quality Sound Short Delay Sharp Roll-off Filter (less than 6/fs)
- High Quality Sound Short Delay Slow Roll-off Filter (less than 6/fs)
- Sharp Roll-off Filter
- Slow Roll-off Filter
Optimized Layout for Sound Quality
SCF
Digital De-emphasis (32kHz, 44.1kHz, 48kHz)
Soft Mute
Digital ATT (256 Steps)
Digital I/F Format: 24Bit MSB justified, 24/20/16Bit LSB justified, I2S
Master Clock: 256fs, 384fs, 512fs or 768fs (Normal Speed Mode)
128fs, 192fs, 256fs or 384fs (Double Speed Mode)
128fs or 192fs (Quad Speed Mode)
THD+N: -100dB
Dynamic Range: 111dB
High Tolerance to Clock Jitter
Power Supply: 4.75 ∼ 5.25V
Package: 16pin TSSOP (6.4mm x 5.0mm)
MS1408-E-01
-
1-
2012/05
http://www.Datasheet4U.com
1 page  
[AK4482]
ANALOG CHARACTERISTICS
(Ta = 25°C; VDD = 5.0V; fs = 44.1kHz; BICK = 64fs; Signal Frequency = 1kHz; 24bit Input Data; Measurement
frequency = 20Hz ∼ 20kHz; RL ≥2kΩ; unless otherwise specified)
Parameter
min typ max Unit
Resolution
24 Bits
Dynamic Characteristics
(Note 3)
THD+N
fs=44.1kHz
0dBFS
- 100 -90 dB
BW=20kHz
-60dBFS
-48 - dB
fs=96kHz
0dBFS
-9 7 -90 dB
BW=40kHz
-60dBFS
-45 - dB
fs=192kHz
0dBFS
-9 7 - dB
BW=40kHz
-60dBFS
-45 - dB
Dynamic Range (-60dBFS with A-weighted) (Note 4) 10
5
111
dB
S/N (A-weighted)
(Note 5) 10
5
111
dB
Interchannel Isolation (1kHz)
90 110
dB
Interchannel Gain Mismatch
0.2 0.5 dB
DC Accuracy
Gain Drift
100 - ppm/°C
Output Voltage
(Note 6)
±2.25
±2.4
±2.55
Vpp
Load Resistance
(Note 7) 2
kΩ
Power Supplies
Power Supply Current (VDD)
Normal Operation (PDN = “H”, fs=44.1kHz)
20 30 mA
Double Operation (PDN = “H”, fs=96kHz)
24 36 mA
Quad Operation (PDN = “H”, fs=192kHz)
30 45 mA
Power-Down Mode (PDN = “L”)
(Note 8)
10 100 µA
Note 3. Measured by Audio Precision, System Two. Refer to the evaluation board manual.
Note 4. 100dB at 16bit data.
Note 5. S/N does not depend on input data size.
Note 6. Full-scale voltage(0dB). Output voltage scales with the VDD voltage.
AOUT (typ.@0dB) = (AOUT+) - (AOUT-) = ±2.4Vpp×VDD/5
Note 7. Regarding Load Resistance, AC load is 4kΩ (min) with a DC cut capacitor.
Note 8. All digital input pins including (MCLK, BICK and LRCK) are fixed to VDD or VSS.
MS1408-E-01
-
5-
2012/05
5 Page 
[AK4482]
OPERATION OVERVIEW
■ System Clock
The external clocks, which are required to operate the AK4482, are MCLK, BICK and LRCK. MCLK should be
synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. There are two modes for setting MCLK frequency, Manual Setting Mode and Auto Setting Mode.
In manual setting mode (ACKS bit = “0”: Register 00H), sampling speed is set by DFS1-0 bits (Table 1) and the MCLK
frequency in each speed mode is set automatically (Table 2~Table 4). The AK4482 is in auto setting mode when a reset is
released (PDN = “↑”). In auto setting mode, sampling speed and MCLK frequency are detected automatically (Table 5).
Then the initial master clock is set to the appropriate frequency (Table 6) so that DIF1-0 bits setting are not necessary.
The AK4482 is automatically placed in power saving mode when MCLK or LRCK is stopped during normal operation,
and the analog output goes to AVDD/2 (typ). When MCLK and LRCK are input again, the AK4482 is powered up. After
exiting reset following power-up, the AK4482 is not fully operational until MCLK and LRCK are input.
DFS1 bit
00
01
10
DFS0 bit
Sampling Rate (fs)
Normal Speed Mode
8kHz~54kHz
Double Speed Mode
60kHz~108kHz
Quad Speed Mode
120kHz~216kHz
(default)
Table 1. Sampling Speed (Manual Setting Mode)
LRCK MCLK
fs 256fs 3
32.0kHz 8.1920MHz
44.1kHz 11 .2896MHz
48.0kHz 12 .2880MHz
84fs 5
12.2880MHz
16.9344MHz
18.4320MHz
12fs 7
16.3840MHz
22.5792MHz
24.5760MHz
68fs
24.5760MHz
33.8688MHz
36.8640MHz
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK MCLK
fs 128fs 1
88.2kHz 11 .2896MHz
96.0kHz 12 .2880MHz
92fs 2
16.9344MHz
18.4320MHz
56fs 3
22.5792MHz
24.5760MHz
84fs
33.8688MHz
36.8640MHz
BICK
64fs
5.6448MHz
6.1440MHz
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
LRCK MCLK
fs 128fs
176.4kHz 22.5792MHz
192.0kHz 24 .5760MHz
192fs
33.8688MHz
36.8640MHz
BICK
64fs
11.2896MHz
12.2880MHz
Table 4. System Clock Example (Quad Speed Mode @Manual Setting Mode)
MS1408-E-01
-
11 -
2012/05
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet AK4482.PDF ] | |
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