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PDF AK1542A Data sheet ( Hoja de datos )
| Número de pieza | AK1542A | |
| Descripción | 20 to 600MHz Integer-N Frequency Synthesizer | |
| Fabricantes | AKM | |
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[AK1542A]
AK1542A
20 to 600MHz Integer-N Frequency Synthesizer
1. Overview
Consisting a highly accurate charge pump that supports current adjustment in 9 steps, a reference divider, a programmable
divider and a dual-modulus prescaler (P/P+1), the AK1542A provides high performance, low consumption current and small
footprint for a wide range of frequency conversions . This synthesizer also has two general-purpose output pins which allow it
to be used to control the RF front end.
An ideal Phase Locked Loop (PLL) can be achieved by combining the AK1542A with the external loop filter and VCO (Voltage
Controlled Oscillator). Access to the registers is controlled via a 3-wire serial interface. The operating supply voltage is from
2.7 to 5.5V; and the supply voltage for the charge pump and that for the serial interface can be driven separately.
2. Features
Operating frequency:
20 to 600MHz
Programmable charge pump current:
158 to 2528A typical
The charge pump current can be changed in 9 steps; and the current
range can be adjusted by the external resistance.
Two current settings can be specified with the register and switched
over from one to another using the timer.
Supply Voltage:
2.7 to 5.5 V (PVDD pin)
Separate power supply for the charge pump: PVDD to 5.5V (CPVDD pin)
On-chip power-saving features
On-chip lock detection feature of PLL:
Direct output to the PFD (Phase frequency detector)
or digital filtering output can be selected.
General-purpose output:
It has two general-purpose output ports to control peripheral parts.
Very low consumption current:
2.2mA typical
Package:
24pin QFN (0.5mm pitch, 4mm4mm0.75mm)
Operating temperature:
-40C to 85C
MS1399-E-00
-1-
2012/3
http://www.Datasheet4U.com
1 page  
[AK1542A]
Note 2) The input voltage from the [CPZ] pin is used in the internal circuit. The [CPZ] pin must not be open even when the
fast Lock Up feature is unused.
For the output destination from the [CPZ] pin, see “P.12 Fig.5 Loop Filter Schematic”. The [SWIN] pin could be
open when the fast Lock Up feature is not used.
Note 3) Power down refers to the state where [PDN1]=[PDN2]=”Low” after power-on.
Note 4) TEST1 to 3 must be connected to ground.
AI: Analog input pin
DO: Digital output pin
AO: Analog output pin
P: Power supply pin
AIO: Analog I/O pin
G: Ground pin
DI: Digital input pin
24 23 22 21 20 19
CPVDD 1
18 PVDD
TEST3 2
17 RFINP
TEST1 3
LE 4
TOP
VIEW
16 RFINN
15 VREF
DATA 5
14 DVSS
CLK 6
13 GPO2
7 8 9 10 11 12
Fig. 2 Package Pin Layout
MS1399-E-00
-5-
2012/3
5 Page 
[AK1542A]
8. Block Functional Descriptions
1. Frequency Setup
The following formula is used to calculate the frequency setting for AK1542A.
Frequency setting (external VCO output frequency) = FPFD × N
N
FPFD
P
B
A
: Dividing number N = [ (P × B) + A ]
: Phase detector frequency FPFD = [REFIN] pin input frequency / R counter dividing number
: Prescaler Value (See<Address2>:{Pre[1:0]})
: B (Programmable) counter value (See <Address1>:{B[12:0]})
: A (Swallow) counter value (See <Address1>:{A[5:0]})
Calculation examples
When the [REFIN] pin input frequency is 10MHz, the phase detector frequency FPFD =5kHz and the frequency setting =
460.1MHz;
[The AK1542A Settings]
R=10000000/5000 = 2000 (<Address3> : {R[13:0]}=2000dec)
P=32 (<Address2>:{Pre[1:0]} =10bin)
B=2875 (<Address1>:{B[12:0]} =2875dec)
A=20 (<Address1>:{A[5:0]} =20dec)
Frequency setting = 5000 × [ (32×2875) + 20] = 460.1MHz
Lower limit for setting consecutive dividing numbers
In the AK1542A, it is impossible to set consecutive dividing numbers below the lower limit. The lower limit is calculated by
the following formula;
Nmin=P2-P
For example, in the case of P=16, it can be set 240 and over as consecutive dividing numbers.
MS1399-E-00
- 11 -
2012/3
11 Page | ||
| Páginas | Total 37 Páginas | |
| PDF Descargar | [ Datasheet AK1542A.PDF ] | |
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