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HIP6602 の電気的特性と機能

HIP6602のメーカーはIntersil Corporationです、この部品の機能は「Dual Channel Synchronous-Rectified Buck MOSFET Driver」です。


製品の詳細 ( Datasheet PDF )

部品番号 HIP6602
部品説明 Dual Channel Synchronous-Rectified Buck MOSFET Driver
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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HIP6602 Datasheet, HIP6602 PDF,ピン配置, 機能
NOTP(ORISESLCS6IO6B0ML1EM4,ESINSU®LDB6ES6DT1I4TFAUOD,TRaaEtnNaPdESRWIShOLeDD6eEU6tS1C4ITGBSN) S
Dual Channel Synchronous-Rectified
Buck MOSFET Driver
The HIP6602 is a high frequency, two power channel
MOSFET driver specifically designed to drive four power
N-Channel MOSFETs in a synchronous-rectified buck
converter topology. These drivers combined with a HIP63xx
series of Multi-Phase Buck PWM controller and Intersil’s
UltraFETs® form a complete core voltage regulator solution
for advanced microprocessors.
The HIP6602 drives both upper and lower gates over a
range of 5V to 12V. This drive-voltage flexibility provides the
advantage of optimizing applications involving trade-offs
between switching losses and conduction losses.
The output drivers in the HIP6602 have the capacity to
efficiently switch power MOSFETs at high frequencies. Each
driver is capable of driving a 3000pF load with a 30ns
propagation delay and 50ns transition time. This device
implements bootstrapping on the upper gates with only a
single external capacitor required for each power channel.
This reduces implementation complexity and allows the use
of higher performance, cost effective, N-Channel MOSFETs.
Adaptive shoot-through protection is integrated to prevent
both MOSFETs from conducting simultaneously.
Ordering Information
TEMP. RANGE
PART NUMBER
(°C)
PACKAGE PKG. NO.
HIP6602CB
0 to 85
14 Ld SOIC M14.15
HIP6602CB-T
14 Ld SOIC Tape and Reel
August 20 00
HIP6602
FN4838.1
Features
• Drives Four N-channel MOSFETs
• Adaptive Shoot-Through Protection
• Internal Bootstrap Devices
• Supports High Switching Frequency
- Fast Output Rise Time
- Propagation Delay 30ns
• Small 14-Lead SOIC Package
• 5V to 12V Gate-Drive Voltages for Optimal Efficiency
• Three-State Input for Bridge Shutdown
• Supply Under-Voltage Protection
Applications
• Core Voltage Supplies for Intel Pentium® III and AMD®
AthlonTM Microprocessors.
• High Frequency Low Profile DC/DC Converters
• High Current Low Voltage DC/DC Converters
Pinout
HIP6602CB
(SOIC)
TOP VIEW
PWM1 1
PWM2 2
GND 3
LGATE1 4
PVCC 5
PGND 6
LGATE2 7
14 VCC
13 PHASE1
12 UGATE1
11 BOOT1
10 BOOT2
9 UGATE2
8 PHASE2
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright © Intersil Corporation 2000, 2005
® ® http://www.Datasheet4U.com
Pentium is a registered trademark of Intel Corporation.; AMD is a registered trademark of Advanced Micro Devices, Inc.
UltraFET® is a registered trademark of Intersil Corporation. Athlon™ is a trademark of Advanced Micro Devices, Inc.

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HIP6602 pdf, ピン配列
HIP6602
Typical Application - 4 Channel Converter Using a HIP6303 and HIP6602 Gate Driver
+12V
VCC
BOOT1
UGATE1
PHASE1
+12V
+5V
PGOOD
EN
VID
FB COMP
VSEN
VCC
ISEN1
PWM1
PWM2
MAIN ISEN2
CONTROL
HIP6303
LGATE1
DUAL
DRIVER
HIP6602
PVCC
+5V/12V
BOOT2
+12V
PWM1
PWM2
GND
UGATE2
PHASE2
LGATE2
PGND
ISEN3
FS/DIS
PWM3
PWM4
GND ISEN4
+12V
VCC
BOOT3
UGATE3
PHASE3
+12V
LGATE3
DUAL
DRIVER
HIP6602
PVCC
+5V/12V
BOOT4
+12V
PWM3
PWM4
UGATE4
PHASE4
LGATE4
GND
PGND
+VCORE
3


3Pages


HIP6602 電子部品, 半導体
HIP6602
A falling transition on PWM indicates the turn-off of the
upper MOSFET and the turn-on of the lower MOSFET. A
short propagation delay [TPDLUGATE] is encountered
before the upper gate begins to fall [TFUGATE]. Again, the
adaptive shoot-through circuitry determines the lower gate
delay time, TPDHLGATE. The PHASE voltage is monitored
and the lower gate is allowed to rise after PHASE drops
below 0.5V. The lower gate then rises [TRLGATE], turning
on the lower MOSFET.
Three-State PWM Input
A unique feature of the HIP6602 drivers is the addition of a
shutdown window to the PWM input. If the PWM signal
enters and remains within the shutdown window for a set
holdoff time, the output drivers are disabled and both
MOSFET gates are pulled and held low. The shutdown state
is removed when the PWM signal moves outside the
shutdown window. Otherwise, the PWM rising and falling
thresholds outlined in the ELECTRICAL SPECIFICATIONS
determine when the lower and upper gates are enabled.
Adaptive Shoot-Through Protection
The drivers incorporate adaptive shoot-through protection to
prevent upper and lower MOSFETs from conducting
simultaneously and shorting the input supply. This is
accomplished by ensuring the falling gate has turned off one
MOSFET before the other is allowed to rise.
During turn-off of the lower MOSFET, the LGATE voltage is
monitored until it reaches a 1.0V threshold, at which time the
UGATE is released to rise. Adaptive shoot-through circuitry
monitors the PHASE voltage during UGATE turn-off. Once
PHASE has dropped below a threshold of 0.5V, the LGATE
is allowed to rise. If the PHASE does not drop below 0.5V
within 250ns, LGATE is allowed to rise. This is done to
generate the bootstrap refresh signal. PHASE continues to
be monitored during the lower gate rise time. If the PHASE
voltage exceeds the 0.5V threshold during this period and
remains high for longer than 2µs, the LGATE transitions low.
This is done to make the lower MOSFET emulate a diode.
Both upper and lower gates are then held low until the next
rising edge of the PWM signal.
Power-On Reset (POR) Function
During initial start-up, the VCC voltage rise is monitored and
gate drives are held low until a typical VCC rising threshold
of 9.95V is reached. Once the rising VCC threshold is
exceeded, the PWM input signal takes control of the gate
drives. If VCC drops below a typical VCC falling threshold of
9.2V during operation, then both gate drives are again held
low. This condition persists until the VCC voltage exceeds
the VCC rising threshold.
Internal Bootstrap Device
Both drivers feature an internal bootstrap device. Simply
adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 5V. The bootstrap capacitor can be
chosen from the following equation:
CBOOT ≥ ∆--Q-V-G-B-AO----T-O--E--T----
Where QGATE is the amount of gate charge required to fully
charge the gate of the upper MOSFET. The VBOOT term is
defined as the allowable droop in the rail of the upper drive.
As an example, suppose a HUF76139 is chosen as the
upper MOSFET. The gate charge, QGATE, from the data
sheet is 65nC for a 10V upper gate drive. We will assume a
200mV droop in drive voltage over the PWM cycle. We find
that a bootstrap capacitance of at least 0.325µF is required.
The next larger standard value capacitance is 0.33µF.
Gate Drive Voltage Versatility
The HIP6602 provides the user flexibility in choosing the
gate drive voltage. Simply applying a voltage from 5V up to
12V on PVCC will set both driver rail voltages.
Power Dissipation
Package power dissipation is mainly a function of theswitching
frequency and total gate chargeof the selected MOSFETs.
Calculating the power dissipation in the driver for a desired
application is critical to ensuring safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperatureof 125°C. The maximumallowable IC power
dissipation for the 14 lead SOIC package is approximately
1000mW. Improvements in thermal transfer may be gani ed by
increasing the PC board copper area around the HIP6602.
Adding a ground pad under the ICto help transfer heat to the
outer peripheral of the board wil help. Alsokeeping the leads to
the IC as wide as possible and widening this these leads as
soon as possible to further enhance heat transfer will also help.
When designing the driver into an application, it is
recommended that the following calculation be performed to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total chip power dissipation is
approximated as:
[ ]P = 1.05 x fSW x VPVCC
3_
2
(QU1
+
QU2)
+
(QL1
+
QL2)
+ IDDQ x VCC
where fsw is the switching frequency of the PWM signal. QU
and QL is the upper and lower gate charge determined by
MOSFET selection and any external capacitance added to
the gate pins. The IDDQ VCC product is the quiescent power
of the driver and is typically 40mW.
The 1.05 term is a correction factor derived from the
following characterization. The base circuit for characterizing
the drivers for different loading profiles and frequencies is
provided. CU and CL are the upper and lower gate load
capacitors. Decoupling capacitors [0.15µF] are added to the
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共有リンク

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