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74VHC1G50 の電気的特性と機能

74VHC1G50のメーカーはFirst Siliconです、この部品の機能は「Noninverting Buffer / CMOS Logic Level Shifter」です。


製品の詳細 ( Datasheet PDF )

部品番号 74VHC1G50
部品説明 Noninverting Buffer / CMOS Logic Level Shifter
メーカ First Silicon
ロゴ First Silicon ロゴ 




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74VHC1G50 Datasheet, 74VHC1G50 PDF,ピン配置, 機能
SEMICONDUCTOR
TECHNICAL D ATA
FC74VHC1G50
Noninverting Buffer / CMOS Logic Level Shifter
FC74VHC1G50 is a single gate noninverting buffer fabricated with silicon gate CMOS technology.
It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.
The FC74VHC1G50 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage.
This allows the 74VHC1G50 to be used to interface 5 V circuits to 3 V circuits.
High Speed: t PD = 3.5 ns (Typ) at V CC = 5 V
Low Power Dissipation: I CC = 2 uA (Max) at TA = 25°C
TTL–Compatible Inputs: V IL = 0.8 V; V IH = 2.0 V
CMOS–Compatible Outputs: V OH > 0.8 V CC ;
V OL < 0.1 V CC @Load
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
Pin and Function Compatible with Other Standard Logic Families
Chip Complexity: FETs = 104; Equivalent Gates = 26
5
4
1
2
3
SC–70/SC–88A/SOT–353
DF SUFFIX
MARKING DIAGRAMS
VLd
Pin 1
d = Date Code
PIN ASSIGNMENT
1 NC
2 IN A
3 GND
4 OUT Y
5 V CC
Figure 1. Pinout (Top View)
Figure 2. Logic Symbol
201.09. 23
Revision No : 0
FUNCTION TABLE
Inputs
A
L
H
Output
Y
L
H
1/4
Free Datasheet http://www.Datasheet4U.com

1 Page





74VHC1G50 pdf, ピン配列
FC74VHC1G50
DC ELECTRICAL CHARACTERISTICS
Symbol
V IH
Parameter
Minimum High–Level
Input Voltage
Test Conditions
V L Maximum Low–Level
Input Voltage
V OH Minimum High–Level V N = V H or V L
Output Voltage
I OH = – 50 µA
V N = V IH or V L
V N = V H or V L
I OH = –4 mA
I OH = –8 mA
V OL Maximum Low–Level
V N = V H or V L
Output Voltage
I OL = 50 µA
V N = V IH or V L
V N = V H or V L
I OL = 4 mA
I OL = 8 mA
I IN Maximum Input
V IN = 5.5 V or GND
Leakage Current
I CC Maximum Quiescent
V IN = V CC or GND
Supply Current
I CCT Quiescent Supply
Input: V IN = 3.4 V
Current
I OPD Output Leakage
V OUT = 5.5 V
Current
V CC T A = 25°C T A < 85°C –55°C<TA<125°C
(V) Min Typ Max Min Max Min Max Unit
2.0 1.5
1.5 1.5
V
3.0 2.1
2.1 2.1
4.5 3.15
3.15
3.15
5.5 3.85
3.85
3.85
2.0 0.5 0.5 0.5 V
3.0 0.9 0.9 0.9
4.5 1.35 1.35 1.35
5.5 1.65 1.65 1.65
V
3.0 2.9 3.0
2.9 2.9
4.5 4.4 4.5
4.4 4.4
3.0 2.58
4.5 3.94
2.48 2.34
3.80 3.66
3.0 0.0 0.1 0.1 0.1
4.5 0.0 0.1 0.1 0.1
V
3.0
4.5
0 to5.5
0.36
0.36
±0.1
0.44
0.44
±1.0
0.52
0.52
±1.0
µA
5.5 2.0 20 40 µA
5.5 1.35 1.50 1.65 mA
0.0
0.5 5.0
10 µA
AC ELECTRICAL CHARACTERISTICS C load = 50 pF, Input t r = t f = 3.0 ns
Symbol Parameter
Test Conditions
T A = 25°C
T A < 85°C –55°C<TA<125°C
Min Typ Max Min Max Min Max Unit
t PLH ,
t PHL
Maximum
Propagation Delay,
Input A to Y
V CC = 3.3± 0.3 V C L = 15 pF
C L = 50 pF
4.5 10.0
6.3 13.5
11.0 13.0 ns
15.0 17.5
C N Maximum Input
Capacitance
V CC = 5.0± 0.5 V C L = 15 pF
C L = 50 pF
3.5 6.7
4.3 7.7
5 10
7.5 8.5
8.5 9.5
10 10 pF
C PD Power Dissipation Capacitance (Note 6)
Typical @ 2C, V CC = 5.0 V
12
pF
6. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without
.load. Average operating current can be obtained by the equation: I CC(OPR) = C PD V CC f in + I CC C PD is used to determine the no–
load dynamic power consumption; P D = C PD V CC 2 f in + I CC V CC .
2011. 09. 23
Revision No : 0
3/4
Free Datasheet http://www.Datasheet4U.com


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部品番号部品説明メーカ
74VHC1G50

Noninverting Buffer / CMOS Logic Level Shifter

First Silicon
First Silicon


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