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C8051F59xのメーカーはSilicon Laboratoriesです、この部品の機能は「Mixed Signal ISP Flash MCU Family」です。 |
部品番号 | C8051F59x |
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部品説明 | Mixed Signal ISP Flash MCU Family | ||
メーカ | Silicon Laboratories | ||
ロゴ | |||
このページの下部にプレビューとC8051F59xダウンロード(pdfファイル)リンクがあります。 Total 30 pages
Analog Peripherals
- 12-Bit ADC
• Up to 200 ksps
• Up to 32 external single-ended inputs
• VREF from on-chip VREF, external pin or VDD
• Internal or external start of conversion source
• Built-in temperature sensor
- Three Comparators
• Programmable hysteresis and response time
• Configurable as interrupt or reset source
• Low current
On-Chip Debug
- On-chip debug circuitry facilitates full speed, non-
intrusive in-system debug (no emulator required)
- Provides breakpoints, single stepping,
inspect/modify memory and registers
- Superior performance to emulation systems using
ICE-chips, target pods, and sockets
- Low cost, complete development kit
Supply Voltage 1.8 to 5.25 V
- Typical operating current: 15 mA at 50 MHz;
Typical stop mode current: 230 µA
High-Speed 8051 µC Core
- Pipelined instruction architecture; executes 70% of
instructions in 1 or 2 system clocks
- Up to 50 MIPS throughput with 50 MHz clock
- Expanded interrupt handler
Automotive Qualified
- Temperature Range: –40 to +125 °C
C8051F58x/F59x
Mixed Signal ISP Flash MCU Family
Memory
- 8448 bytes internal data RAM (256 + 8192 XRAM)
- 128 or 96 kB Banked Flash; In-system programma-
ble in 512-byte Sectors
- External 64 kB data memory interface programma-
ble for multiplexed or non-multiplexed mode
Digital Peripherals
- 40, 33, or 25 Port I/O; All 5 V push-pull with high
sink current
- CAN 2.0 Controller—no crystal required
- LIN 2.1 Controller (Master and Slave capable); no
crystal required
- Two Hardware enhanced UARTs, SMBus™, and
enhanced SPI™ serial ports
- Six general purpose 16-bit counter/timers
- Two 16-Bit programmable counter array (PCA)
peripherals with six capture/compare modules each
and enhanced PWM functionality
Clock Sources
- Internal 24 MHz with ±0.5% accuracy for CAN and
master LIN operation.
- External oscillator: Crystal, RC, C, or clock
(1 or 2 pin modes)
- Can switch between clock sources on-the-fly;
useful in power saving modes
Packages
- 48-Pin QFP/QFN (C8051F580/1/4/5)
- 40-Pin QFN (C8051F588/9-F590/1)
- 32-Pin QFP/QFN (C8051F582/3/6/7)
ANALOG
PERIPHERALS
A 12-bit
M
U
200 ksps
X ADC
TEMP
SENSOR
Voltage VREG
Comparators 0-2 VREF
DIGITAL I/O
UART 0-1
SMBus
SPI
PCA x 2
Timers 0-5
CAN
LIN
Ports 0-4
Crossbar
External
Memory
Interface
24 MHz PRECISION
INTERNAL OSCILLATOR
2x Clock Multiplier
HIGH-SPEED CONTROLLER CORE
128 kB
ISP FLASH
FLEXIBLE
INTERRUPTS
8051 CPU
(50 MIPS)
DEBUG
CIRCUITRY
8 kB XRAM
POR WDT
Rev. 1.2 4/11
Copyright © 2011 by Silicon Laboratories C8051F580/1/2/3/4/5/6/7/8/9-F590/1
Free Datasheet http://www.Datasheet4U.com
1 Page C8051F58x/F59x
Table of Contents
1. System Overview ..................................................................................................... 18
2. Ordering Information ............................................................................................... 22
3. Pin Definitions.......................................................................................................... 24
4. Package Specifications ........................................................................................... 32
4.1. QFP-48 Package Specifications........................................................................ 32
4.2. QFN-48 Package Specifications........................................................................ 34
4.3. QFN-40 Package Specifications........................................................................ 36
4.4. QFP-32 Package Specifications........................................................................ 38
4.5. QFN-32 Package Specifications........................................................................ 40
5. Electrical Characteristics ........................................................................................ 42
5.1. Absolute Maximum Specifications..................................................................... 42
5.2. Electrical Characteristics ................................................................................... 43
6. 12-Bit ADC (ADC0) ................................................................................................... 54
6.1. Modes of Operation ........................................................................................... 55
6.1.1. Starting a Conversion................................................................................ 55
6.1.2. Tracking Modes......................................................................................... 55
6.1.3. Timing ....................................................................................................... 56
6.1.4. Burst Mode................................................................................................ 57
6.2. Output Code Formatting .................................................................................... 59
6.2.1. Settling Time Requirements...................................................................... 59
6.3. Selectable Gain ................................................................................................. 60
6.3.1. Calculating the Gain Value........................................................................ 60
6.3.2. Setting the Gain Value .............................................................................. 62
6.4. Programmable Window Detector....................................................................... 68
6.4.1. Window Detector In Single-Ended Mode .................................................. 70
6.5. ADC0 Analog Multiplexer .................................................................................. 72
7. Temperature Sensor ................................................................................................ 74
8. Voltage Reference.................................................................................................... 75
9. Comparators............................................................................................................. 77
9.1. Comparator Multiplexer ..................................................................................... 85
10. Voltage Regulator (REG0) ..................................................................................... 89
11. CIP-51 Microcontroller........................................................................................... 91
11.1. Performance .................................................................................................... 91
11.2. Instruction Set.................................................................................................. 93
11.2.1. Instruction and CPU Timing .................................................................... 93
11.3. CIP-51 Register Descriptions .......................................................................... 97
11.4. Serial Number Special Function Registers (SFRs) ....................................... 101
12. Memory Organization .......................................................................................... 102
12.1. Program Memory........................................................................................... 102
12.1.1. MOVX Instruction and Program Memory .............................................. 104
12.2. Data Memory ................................................................................................. 104
12.2.1. Internal RAM ......................................................................................... 105
12.2.1.1. General Purpose Registers .......................................................... 105
Rev. 1.2
3
Free Datasheet http://www.Datasheet4U.com
3Pages C8051F58x/F59x
21.4. LIN Slave Mode Operation ............................................................................ 217
21.5. Sleep Mode and Wake-Up ............................................................................ 218
21.6. Error Detection and Handling ........................................................................ 218
21.7. LIN Registers................................................................................................. 219
21.7.1. LIN Direct Access SFR Registers Definitions ....................................... 219
21.7.2. LIN Indirect Access SFR Registers Definitions ..................................... 221
22. Controller Area Network (CAN0) ........................................................................ 229
22.1. Bosch CAN Controller Operation................................................................... 230
22.1.1. CAN Controller Timing .......................................................................... 230
22.1.2. CAN Register Access............................................................................ 231
22.1.3. Example Timing Calculation for 1 Mbit/Sec Communication ................ 231
22.2. CAN Registers............................................................................................... 233
22.2.1. CAN Controller Protocol Registers........................................................ 233
22.2.2. Message Object Interface Registers ..................................................... 233
22.2.3. Message Handler Registers.................................................................. 233
22.2.4. CAN Register Assignment .................................................................... 234
23. SMBus................................................................................................................... 237
23.1. Supporting Documents .................................................................................. 238
23.2. SMBus Configuration..................................................................................... 238
23.3. SMBus Operation .......................................................................................... 238
23.3.1. Transmitter Vs. Receiver....................................................................... 239
23.3.2. Arbitration.............................................................................................. 239
23.3.3. Clock Low Extension............................................................................. 239
23.3.4. SCL Low Timeout.................................................................................. 239
23.3.5. SCL High (SMBus Free) Timeout ......................................................... 240
23.4. Using the SMBus........................................................................................... 240
23.4.1. SMBus Configuration Register.............................................................. 240
23.4.2. SMB0CN Control Register .................................................................... 244
23.4.3. Data Register ........................................................................................ 247
23.5. SMBus Transfer Modes................................................................................. 247
23.5.1. Write Sequence (Master) ...................................................................... 248
23.5.2. Read Sequence (Master) ...................................................................... 249
23.5.3. Write Sequence (Slave) ........................................................................ 250
23.5.4. Read Sequence (Slave) ........................................................................ 251
23.6. SMBus Status Decoding................................................................................ 251
24. UART0 ................................................................................................................... 254
24.1. Baud Rate Generator .................................................................................... 254
24.2. Data Format................................................................................................... 256
24.3. Configuration and Operation ......................................................................... 257
24.3.1. Data Transmission ................................................................................ 257
24.3.2. Data Reception ..................................................................................... 257
24.3.3. Multiprocessor Communications ........................................................... 258
25. UART1 ................................................................................................................... 263
25.1. Enhanced Baud Rate Generation.................................................................. 264
25.2. Operational Modes ........................................................................................ 265
6 Rev. 1.2
Free Datasheet http://www.Datasheet4U.com
6 Page | |||
ページ | 合計 : 30 ページ | ||
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部品番号 | 部品説明 | メーカ |
C8051F590 | Mixed Signal ISP Flash MCU Family | Silicon Laboratories |
C8051F591 | Mixed Signal ISP Flash MCU Family | Silicon Laboratories |
C8051F59x | Mixed Signal ISP Flash MCU Family | Silicon Laboratories |