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PDF CY62137VN Data sheet ( Hoja de datos )
| Número de pieza | CY62137VN | |
| Descripción | 2-Mbit (128K x 16) Static RAM | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY62137VN MoBL®
2-Mbit (128K x 16) Static RAM
Features
• Temperature Ranges
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
— Automotive-E: –40°C to 125°C
• High Speed: 55 ns
• Wide voltage range: 2.7V–3.6V
• Ultra-low active, standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Available in Pb-free 44-pin TSOP Type II package
Functional Description[1]
The CY62137VN is a high-performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL®) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that reduces power
consumption by 99% when addresses are not toggling. The
device can also be put into standby mode when deselected
(CE HIGH) or when CE is LOW and both BLE and BHE are
HIGH. The input/output pins (I/O0 through I/O15) are placed in
a high-impedance state when: deselected (CE HIGH), outputs
are disabled (OE HIGH), BHE and BLE are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW, and WE
LOW).Writing to the device is accomplished by taking Chip
Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O0 through
I/O7), is written into the location specified on the address pins
(A0 through A16). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O8 through I/O15) is written into the location
specified on the address pins (A0 through A16).Reading from
the device is accomplished by taking Chip Enable (CE) and
Output Enable (OE) LOW while forcing the Write Enable (WE)
HIGH. If Byte Low Enable (BLE) is LOW, then data from the
memory location specified by the address pins will appear on
I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from
memory will appear on I/O8 to I/O15. See the truth table at the
back of this data sheet for a complete description of read and
write modes.
Logic Block Diagram
A1010
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DATA IN DRIVERS
128K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
COLUMN DECODER
Power-down
Circuit
CE
BHE
BLE
BHE
WE
CE
OE
BLE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06497 Rev. *A
Revised August 3, 2006
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CY62137VN MoBL®
Switching Characteristics Over the Operating Range [6]
55 ns
70 ns
Parameter
Description
Min.
Max.
Min.
Max.
Unit
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
tLZBE (9)
tHZBE
Write Cycle[10, 11]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[7]
OE HIGH to High-Z[7, 8]
CE LOW to Low-Z[7]
CE HIGH to High-Z[7, 8]
CE LOW to Power-up
CE HIGH to Power-down
BHE / BLE LOW to Data Valid
BHE / BLE LOW to Low-Z
BHE / BLE HIGH to High-Z
55 70 ns
55 70 ns
10 10 ns
55 70 ns
25 35 ns
5 5 ns
25 25 ns
10 10 ns
25 25 ns
0 0 ns
55 70 ns
55 70 ns
5 5 ns
25 25 ns
tWC Write Cycle Time
55 70 ns
tSCE
CE LOW to Write End
45 60 ns
tAW
Address Set-up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0 ns
tSA
Address Set-up to Write Start
0
0 ns
tPWE
WE Pulse Width
40 50 ns
tSD
Data Set-up to Write End
25
30
ns
tHD
tHZWE
tLZWE
Data Hold from Write End
WE LOW to High-Z[7, 8]
WE HIGH to Low-Z[7]
0 0 ns
20 25 ns
5 10 ns
tBW
BHE / BLE LOW to End of Write
50
60
ns
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input levels of 0 to VCC typ., and output loading of the specified
IOL/IOH and 30 pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. If both byte enables are toggled together this value is 10 ns.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 001-06497 Rev. *A
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CY62137VN MoBL®
Document History Page
Document Title: CY62137VN MoBL® 2-Mbit (128K x 16) Static RAM
Document Number: 001-06497
Orig. of
REV. ECN NO. Issue Date Change
Description of Change
** 426503 See ECN NXR New Data Sheet
*A 488954 See ECN
NXR Added Automotive product
Updated Ordering Information table
Document #: 001-06497 Rev. *A
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet CY62137VN.PDF ] | |
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