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PDF CY2077 Data sheet ( Hoja de datos )
| Número de pieza | CY2077 | |
| Descripción | High-accuracy EPROM Programmable Single-PLL Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CY2077 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
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CY2077
High-accuracy EPROM Programmable
Single-PLL Clock Generator
Features
■ High-accuracy PLL with 12-bit multiplier and 10-bit divider
■ EPROM programmability
■ 3.3 V or 5 V operation
■ Operating frequency
❐ 390 kHz–133 MHz at 5 V
❐ 390 kHz–100 MHz at 3.3 V
■ Reference input from either a 10–30 MHz fundamental toned
crystal or a 1–75 MHz external clock
■ EPROM selectable TTL or CMOS duty cycle levels
■ Sixteen selectable post-divide options, using either PLL or
reference oscillator/external clock
■ Programmable PWR_DWN or OE pin, with asynchronous or
synchronous modes
■ Low jitter outputs typically
❐ 80 ps at 3.3 V/5 V
■ Controlled rise and fall times and output slew rate
■ Available in both commercial and industrial temperature ranges
■ Factory programmable device options
Logic Block Diagram
PWR_DWN
or OE
XTALOUT[1]
XTALIN
or
external clock
Q
10 bits
HIGH
ACCURACY
PLL
Charge
Pump
VCO
P
12 bits
Configuration
EPROM
MUX
/ 1, 2, 4, 8, 16, 32, 64, 128
CLKOUT
Note
1. When using an external clock source, leave XTALOUT floating.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07210 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 1, 2012
http://www.Datasheet4U.com
1 page  
CY2077
Electrical Characteristics
TA = 0°C to +70°C
Parameter Description
Test Conditions
VIL
VIH
VOL
VOHCMOS
VOHTTL
IIL
IIH
IDD
IDDS[3]
RUP
IOE_CLKOUT
Low-level input voltage
VDD = 4.5 – 5.5 V
VDD = 3.0 – 3.6 V
High-level input voltage
VDD = 4.5 – 5.5 V
VDD = 3.0 – 3.6 V
Low-level output voltage
VDD = 4.5 – 5.5 V, IOL= 16 mA
VDD = 3.0 – 3.6 V, IOL= 8 mA
High-level output voltage CMOS levels VDD = 4.5 – 5.5 V, IOH= –16 mA
VDD = 3.0 – 3.6 V, IOH= –8 mA
High-level output voltage TTL levels VDD = 4.5 – 5.5 V, IOH= –8 mA
Input low current
VIN = 0 V
Input high current
VIN = VDD
Power supply current Unloaded
VDD = 4.5 – 5.5 V, output
frequency <= 133 MHz
VDD = 3.0 – 3.6 V, output
frequency <= 100 MHz
Stand-by current (PD = 0)
Input pull up resistor
CLKOUT pull down current
VDD = 4.5 – 5.5 V
VDD = 3.0 – 3.6 V
VDD = 4.5 – 5.5 V, VIN = 0 V
VDD = 4.5 – 5.5 V, VIN = 0.7 VDD
VDD = 5.0
Min
–
–
2.0
0.7 VDD
–
–
VDD – 0.4
VDD – 0.4
2.4
–
–
–
–
–
–
1.1
50
–
Typ Max
– 0.8
– 0.2 VDD
––
––
– 0.4
– 0.4
––
––
––
– 10
–5
– 45
– 25
25 100
10 50
3.0 8.0
100 200
20 –
Unit
V
V
V
V
V
V
V
V
V
A
A
mA
mA
A
A
M
k
A
Note
3. If external reference is used, it is required to stop the reference (set reference to LOW) during power down.
Document Number: 38-07210 Rev. *G
Page 5 of 17
http://www.Datasheet4U.com
5 Page 
CY2077
Typical Duty Cycle[9] Trends for CY2077
Figure 9. Duty Cycle vs. VDD over Temperatures
Duty Cycle vs. VDD over Temperature
(TTL Duty Cycle Output, Fout=50MHz, Cload =
50pF)
Duty Cycle vs. VDD over Temperature
(CMOS Duty Cycle Ouput, Fout=50MHz,
Cload=50pF)
55.00
53.00
51.00
49.00
47.00
45.00
4.0
4.5 5.0 5.5
VDD (V)
6.0
-40C
25C
85C
55.00
53.00
51.00
49.00
47.00
45.00
2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDD (v)
-40C
25C
85C
Figure 10. Duty Cycle vs. Output Load
Duty Cycle vs. CLoad with Various VDD
(Fout = 50MHz, Temp = 25C)
55.00
53.00
51.00
49.00
47.00
45.00
10 15 20 25 30 35 40 45 50 55
Cload (pF)
VDD=4.5V
VDD=5.0V
VDD=5.5V
Figure 11. Duty Cycle vs. Output Frequency over Temperatures
Output Duty Cycle vs. Fout over Temperature
(Vdd = 5V, Cload = 15pF)
55.00%
54.00%
53.00%
52.00%
51.00%
50.00%
25C
85C
-40C
20 30 40 50 60 70 80
Output Frequency (MHz)
Note
9. Duty cycle is measured at 1.4 V for TTL output and 0.5 VDD for CMOS output.
Document Number: 38-07210 Rev. *G
Page 11 of 17
http://www.Datasheet4U.com
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet CY2077.PDF ] | |
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