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74HC374 の電気的特性と機能

74HC374のメーカーはON Semiconductorです、この部品の機能は「Octal 3-State Non-Inverting D Flip-Flop」です。


製品の詳細 ( Datasheet PDF )

部品番号 74HC374
部品説明 Octal 3-State Non-Inverting D Flip-Flop
メーカ ON Semiconductor
ロゴ ON Semiconductor ロゴ 




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74HC374 Datasheet, 74HC374 PDF,ピン配置, 機能
74HC374
Octal 3−State Non−Inverting
D Flip−Flop
HighPerformance SiliconGate CMOS
The 74HC374 is identical in pinout to the LS374. The device inputs
are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
Data meeting the setup time is clocked to the outputs with the rising
edge of the clock. The Output Enable input does not affect the states of
the flipflops, but when Output Enable is high, the outputs are forced
to the highimpedance state; thus, data may be stored even when the
outputs are not enabled.
The HC374 is identical in function to the HC574A which has the
input pins on the opposite side of the package from the output. This
device is similar in function to the HC534A which has inverting
outputs.
Features
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 266 FETs or 66.5 Equivalent Gates
This is a PbFree Device
http://onsemi.com
MARKING
DIAGRAM
20
1
20
TSSOP20
DT SUFFIX
CASE 948E
1
HC
374
ALYW G
G
HC374 = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = PbFree Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2007
March, 2007 Rev. 0
1
Publication Order Number:
74HC374/D
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1 Page





74HC374 pdf, ピン配列
74HC374
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VCC DC Supply Voltage (Referenced to GND)
– 0.5 to + 7.0
V
Vin DC Input Voltage (Referenced to GND)
Vout DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
– 0.5 to VCC + 0.5
V
V
Iin DC Input Current, per Pin
±20 mA
Iout DC Output Current, per Pin
±35 mA
ICC DC Supply Current, VCC and GND Pins
PD Power Dissipation in Still Air, TSSOP Package†
±75
450
mA
mW
Tstg Storage Temperature
– 65 to + 150
_C
TL Lead Temperature, 1 mm from Case for 10 Seconds
(TSSOP Package)
260
_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
VCC
Vin, Vout
TA
tr, tf
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
Min
2.0
0
– 55
0
0
0
Max
6.0
VCC
+ 125
1000
500
400
Unit
V
V
_C
ns
http://onsemi.com
3
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3Pages


74HC374 電子部品, 半導体
74HC374
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
Figure
VCC – 55 to 25_C
v 85_C
(V) Min Max Min Max
v 125_C
Min Max
Unit
tsu Minimum Setup Time, Data to Clock
3 2.0 50 65 75 ns
3.0 40 50 60
4.5 10 13 15
6.0 9
11 13
th Minimum Hold Time, Clock to Data
3 2.0 5.0 5.0 5.0
3.0 5.0 5 0 5.0
4.5 5.0 5.0 5.0
6.0 5.0 5.0 5.0
ns
tw Minimum Pulse Width, Clock
1 2.0 60 75 90 ns
3.0 23 27 32
4.5 12 15 18
6.0 10 13 15
tr, tf Maximum Input Rise and Fall Times
1 2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
SWITCHING WAVEFORMS
CLOCK
Q
tr
90%
50%
tf
10%
tW
1/fmax
tPLH
90%
50%
10%
tTLH
tPHL
tTHL
Figure 1.
VCC
GND
OUTPUT
ENABLE
Q
Q
50%
tPZL
50%
tPLZ
tPZH tPHZ
50%
Figure 2.
VCC
GND
HIGH
IMPEDANCE
10% VOL
90% VOH
HIGH
IMPEDANCE
DATA
CLOCK
VALID
50%
tsu th
50%
Figure 3.
VCC
GND
VCC
GND
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6 Page



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