PDF MX25V8006E Data sheet ( Hoja de datos )

Número de pieza	MX25V8006E
Descripción	8M-BIT [x 1/x 2] CMOS SERIAL FLASH
Fabricantes	MACRONIX
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No Preview Available ! MX25V8006E MX25V8006E DATASHEET P/N: PM1646 REV. 1.4, DEC. 13, 2013 1 http://www.Datasheet4U.com 1 page MX25V8006E GENERAL DESCRIPTION The device features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The four bus signals are a clock input (SCLK), a serial data input (SI), a serial data output (SO), and a chip select (CS#). Serial access to the device is enabled by CS# input. When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output. The device provides sequential read operation on whole chip. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci- fied page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or word basis for erase command is executes on sector, or block, or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in standby mode. The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. PIN CONFIGURATIONS 8-PIN SOP (150mil) CS# SO/SIO1 WP# GND 1 2 3 4 8 VCC 7 HOLD# 6 SCLK 5 SI/SIO0 8-LAND, WSON (6x5mm) CS# SO/SIO1 WP# GND 1 2 3 4 8 VCC 7 HOLD# 6 SCLK 5 SI/SIO0 PIN DESCRIPTION SYMBOL DESCRIPTION CS# Chip Select SI/SIO0 Serial Data Input (for 1 x I/O) / Serial Data Input & Output (for Dual Output mode) SO/SIO1 Serial Data Output (for 1 x I/O) / Serial Data Output (for Dual Output mode) SCLK Clock Input WP# Write Protection HOLD# Hold, to pause the device without deselecting the device VCC + 2.5V Power Supply GND Ground P/N: PM1646 REV. 1.4, DEC. 13, 2013 5 http://www.Datasheet4U.com 5 Page MX25V8006E HOLD FEATURE HOLD# pin signal goes low to hold any serial communications with the device. The HOLD feature will not stop the operation of write status register, programming, or erasing in progress. The operation of HOLD requires Chip Select(CS#) keeping low and starts on falling edge of HOLD# pin signal while Serial Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Se- rial Clock(SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 2. Figure 2. Hold Condition Operation SCLK HOLD# Hold Condition (standard use) Hold Condition (non-standard use) The Serial Data Output (SO) is high impedance, both Serial Data Input (SI) and Serial Clock (SCLK) are don't care during the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device. To re-start communication with chip, the HOLD# must be at high and CS# must be at low. P/N: PM1646 11 REV. 1.4, DEC. 13, 2013 http://www.Datasheet4U.com 11 Page

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