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MX25U1001E の電気的特性と機能

MX25U1001EのメーカーはMACRONIXです、この部品の機能は「FLASH MEMORY」です。


製品の詳細 ( Datasheet PDF )

部品番号 MX25U1001E
部品説明 FLASH MEMORY
メーカ MACRONIX
ロゴ MACRONIX ロゴ 




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MX25U1001E Datasheet, MX25U1001E PDF,ピン配置, 機能
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
MX25U5121E, MX25U1001E
DATASHEET
P/N: PM1980
REV. 0.00, OCT. 11, 2013
1
http://www.Datasheet4U.com

1 Page





MX25U1001E pdf, ピン配列
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
Figure 3. Program/Erase flow with read array data..................................................................................... 20
12. ELECTRICAL SPECIFICATIONS......................................................................................................................... 21
12-1. ABSOLUTE MAXIMUM RATINGS........................................................................................................... 21
Figure 4. Maximum Negative Overshoot Waveform.................................................................................... 21
12-2. CAPACITANCE TA = 25°C, f = 1.0 MHz................................................................................................... 21
Figure 5. Maximum Positive Overshoot Waveform..................................................................................... 21
Figure 6. Input Test Waveforms and Measurement Level........................................................................... 22
Figure 7. Output Loading............................................................................................................................. 22
Table 8. DC CHARACTERISTICS............................................................................................................ 23
Table 9. AC CHARACTERISTICS ........................................................................................................... 24
13. Timing Analysis................................................................................................................................................... 25
Figure 8. Serial Input Timing........................................................................................................................ 25
Figure 9. Output Timing............................................................................................................................... 25
Figure 10. WP# Disable Setup and Hold Timing during WRSR when SRWD=1......................................... 26
Figure 11. Write Enable (WREN) Sequence (Command 06)....................................................................... 26
Figure 12. Write Disable (WRDI) Sequence (Command 04)....................................................................... 26
Figure 13. Read Identification (RDID) Sequence (Command 9F)............................................................... 27
Figure 14. Read Status Register (RDSR) Sequence (Command 05)......................................................... 28
Figure 15. Write Status Register (WRSR) Sequence (Command 01)........................................................ 28
Figure 16. Read Data Bytes (READ) Sequence (Command 03)................................................................ 28
Figure 17. Read at Higher Speed (FAST_READ) Sequence (Command 0B)............................................ 29
Figure 18. Dual Read Mode Sequence (Command 3B).............................................................................. 29
Figure 19. 4 x I/O Read Mode Sequence (Command EB).......................................................................... 30
Figure 20. Sector Erase (SE) Sequence (Command 20)........................................................................... 30
Figure 21. Block Erase (BE) Sequence (Command D8 or 52)................................................................... 31
Figure 22. Chip Erase (CE) Sequence (Command 60 or C7).................................................................... 31
Figure 23. Page Program (PP) Sequence (Command 02)......................................................................... 31
Figure 24. Deep Power Down (DP) Sequence (Command B9).................................................................. 32
Figure 25. Release from Deep Power Down (RDP) Sequence (Command AB)......................................... 32
Figure 26. Power-Up Timing........................................................................................................................ 33
Table 10. Power-Up Timing....................................................................................................................... 33
13-1. INITIAL DELIVERY STATE....................................................................................................................... 33
14. OPERATING CONDITIONS.................................................................................................................................. 34
Figure 27. AC Timing at Device Power-Up.................................................................................................. 34
Figure 28. Power-Down Sequence.............................................................................................................. 35
15. ERASE AND PROGRAMMING PERFORMANCE............................................................................................... 36
17. DATA RETENTION .............................................................................................................................................. 36
16. LATCH-UP CHARACTERISTICS......................................................................................................................... 36
18. ORDERING INFORMATION................................................................................................................................. 37
19. PART NAME DESCRIPTION................................................................................................................................ 38
20. PACKAGE INFORMATION................................................................................................................................... 39
P/N: PM1980
REV. 0.00, OCT. 11, 2013
3
http://www.Datasheet4U.com


3Pages


MX25U1001E 電子部品, 半導体
3. PIN CONFIGURATIONS
8-PIN SOP (150mil)
CS#
SO/SIO1
WP#/SIO2
GND
1
2
3
4
8 VCC
7 HOLD#/SIO3
6 SCLK
5 SI/SIO0
8-PIN TSSOP (173mil)
CS#
SO/SIO1
WP#/SIO2
GND
1
2
3
4
8 VCC
7 HOLD#/SIO3
6 SCLK
5 SI/SIO0
8-LAND USON (2x3mm)
CS#
SO/SIO1
WP#/SIO2
GND
1
2
3
4
8 VCC
7 HOLD#/SIO3
6 SCLK
5 SI/SIO0
ADVANCED INFORMATION
MX25U5121E
MX25U1001E
4. PIN DESCRIPTION
SYMBOL DESCRIPTION
CS# Chip Select
SI/SIO0
SO/SIO1
Serial Data Input or Serial Data
Input/Output for 2 x I/O read mode
and 4 x I/O read mode
Serial Data Output or Serial Data
Input/Output for 2 x I/O read mode
and 4 x I/O read mode
SCLK Clock Input
Pause the chip without diselecting the
HOLD#/SIO3 chip or Serial Data Input/Output for
4 x I/O read mode
Hardware write protection or Serial
WP#/SIO2 Data Input/Output for 4 x I/O read
mode
VCC
+1.8V Power Supply
GND Ground
P/N: PM1980
REV. 0.00, OCT. 11, 2013
6
http://www.Datasheet4U.com

6 Page



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部品番号部品説明メーカ
MX25U1001E

FLASH MEMORY

MACRONIX
MACRONIX


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