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ADP7104 の電気的特性と機能

ADP7104のメーカーはAnalog Devicesです、この部品の機能は「CMOS LDO」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADP7104
部品説明 CMOS LDO
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADP7104 Datasheet, ADP7104 PDF,ピン配置, 機能
Data Sheet
20 V, 500 mA, Low Noise, CMOS LDO
ADP7104
FEATURES
Input voltage range: 3.3 V to 20 V
Maximum output current: 500 mA
Low noise: 15 µV rms for fixed output versions
PSRR performance of 60 dB at 10 kHz, VOUT = 3.3 V
Reverse current protection
Low dropout voltage: 350 mV at 500 mA
Initial accuracy: ±0.8%
Accuracy over line, load, and temperature: −2%/+1%
Low quiescent current (VIN = 5 V), IGND= 900 μA with 500 mA load
Low shutdown current: <40 µA at VIN = 12 V, stable with small
1 µF ceramic output capacitor
7 fixed output voltage options: 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V,
5 V, and 9 V
Adjustable output from 1.22 V to VIN − VDO
Foldback current limit and thermal overload protection
User programmable precision UVLO/enable
Power-good indicator
8-lead LFCSP and 8-lead SOIC packages
APPLICATIONS
Regulation to noise sensitive applications: ADC, DAC circuits,
precision amplifiers, high frequency oscillators, clocks,
and PLLs
Communications and infrastructure
Medical and healthcare
Industrial and instrumentation
GENERAL DESCRIPTION
The ADP7104 is a CMOS, low dropout linear regulator that
operates from 3.3 V to 20 V and provides up to 500 mA of
output current. This high input voltage LDO is ideal for
regulation of high performance analog and mixed signal
circuits operating from 19 V to 1.22 V rails. Using an
advanced proprietary architecture, it provides high power
supply rejection, low noise, and achieves excellent line and
load transient response with just a small 1 µF ceramic
output capacitor.
The ADP7104 is available in seven fixed output voltage options
and an adjustable version, which allows output voltages that
range from 1.22 V to VIN − VDO via an external feedback divider.
TYPICAL APPLICATION CIRCUITS
VIN = 8V
CIN +
1µF
ON 100k
OFF
100k
VIN VOUT
SENSE
EN/
UVLO
PG
GND
+ COUT
1µF
VOUT = 5V
100k
PG
Figure 1. ADP7104 with Fixed Output Voltage, 5 V
VIN = 8V
CIN +
1µF
ON 100k
OFF
100k
VIN VOUT
ADJ
EN/
UVLO
PG
GND
40.2k
VOUT = 5V
+ COUT
1µF
13k
100k
PG
Figure 2. ADP7104 with Adjustable Output Voltage, 5 V
The ADP7104 output noise voltage is 15 μV rms and is inde-
pendent of the output voltage. A digital power-good output
allows power system monitors to check the health of the output
voltage. A user programmable precision undervoltage lockout
function facilitates sequencing of multiple power supplies.
The ADP7104 is available in 8-lead, 3 mm × 3 mm LFCSP
and 8-lead SOIC packages. The LFCSP offers a very compact
solution and also provides excellent thermal performance for
applications requiring up to 500 mA of output current in a
small, low-profile footprint.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2011–2012 Analog Devices, Inc. All rights reserved.
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1 Page





ADP7104 pdf, ピン配列
Data Sheet
ADP7104
SPECIFICATIONS
VIN = (VOUT + 1 V) or 3.3 V (whichever is greater), EN = VIN, IOUT = 10 mA, CIN = COUT = 1 µF, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Conditions
Min Typ Max
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT
SHUTDOWN CURRENT
INPUT REVERSE CURRENT
VIN
IGND
IGND-SD
IREV-INPUT
IOUT = 100 µA, VIN = 10 V
IOUT = 100 µA, VIN = 10 V, TJ = −40°C to +125°C
IOUT = 10 mA, VIN = 10 V
IOUT = 10 mA, VIN = 10 V, TJ = −40°C to +125°C
IOUT = 300 mA, VIN = 10 V
IOUT = 300 mA, VIN = 10 V, TJ = −40°C to +125°C
IOUT = 500 mA, VIN = 10 V
IOUT = 500 mA, VIN = 10 V, TJ = −40°C to +125°C
EN = GND, VIN = 12 V
EN = GND, VIN = 12 V, TJ = −40°C to +125°C
EN = GND, VIN = 0 V, VOUT = 20 V
EN = GND, VIN = 0 V, VOUT = 20 V, TJ = −40°C to
+125°C
3.3
20
400
900
450
1050
750
1400
900
1600
40 50
75
0.3
5
OUTPUT VOLTAGE ACCURACY
Fixed Output Voltage Accuracy
Adjustable Output Voltage
Accuracy
LINE REGULATION
LOAD REGULATION 1
ADJ INPUT BIAS CURRENT
SENSE INPUT BIAS CURRENT
DROPOUT VOLTAGE 2
START-UP TIME 3
CURRENT-LIMIT THRESHOLD 4
PG OUTPUT LOGIC LEVEL
PG Output Logic High
PG Output Logic Low
PG OUTPUT THRESHOLD
Output Voltage Falling
Output Voltage Rising
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
VOUT
VADJ
∆VOUT/∆VIN
∆VOUT/∆IOUT
ADJI-BIAS
SENSEI-BIAS
VDROPOUT
tSTART-UP
ILIMIT
IOUT = 10 mA
1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V,
TJ = −40°C to +125°C
IOUT = 10 mA
1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V,
TJ = −40°C to +125°C
VIN = (VOUT + 1 V) to 20 V, TJ = −40°C to +125°C
IOUT = 1 mA to 500 mA
IOUT = 1 mA to 500 mA, TJ = −40°C to +125°C
1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V,
ADJ connected to VOUT
1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V,
SENSE connected to VOUT, VOUT = 1.5 V
IOUT = 10 mA
IOUT = 10 mA, TJ = −40°C to +125°C
IOUT = 150 mA
IOUT = 150 mA, TJ = −40°C to +125°C
IOUT = 300 mA
IOUT = 300 mA, TJ = −40°C to +125°C
IOUT = 500 mA
IOUT = 500 mA, TJ = −40°C to +125°C
VOUT = 5 V
–0.8 +0.8
–2 +1
1.21 1.22 1.23
1.196
1.232
−0.015
0.2
10
+0.015
0.75
1
20
40
100
175
200
325
350
550
1000
625 775 1000
PGHIGH
PGLOW
IOH < 1 µA
IOL < 2 mA
1.0
0.4
PGFALL
PGRISE
−9.2
−6.5
TSSD
TSSD-HYS
TJ rising
150
15
Unit
V
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
%
%
V
V
%/V
%/A
%/A
nA
μA
mV
mV
mV
mV
mV
mV
mV
mV
µs
mA
V
V
%
%
°C
°C
Rev. B | Page 3 of 28
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ADP7104 電子部品, 半導体
ADP7104
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VOUT 1
SENSE/ADJ 2
GND 3
NC 4
ADP7104
TOP VIEW
(Not to Scale)
8 VIN
7 PG
6 GND
5 EN/UVLO
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO
THIS PIN.
2. IT IS HIGHLY RECOMMENDED THAT THE
EXPOSED PAD ON THE BOTTOM OF THE
PACKAGE BE CONNECTED TO THE GROUND
PLANE ON THE BOARD.
Figure 3. LFCSP Package
VOUT 1
8 VIN
SENSE/ADJ 2 ADP7104 7 PG
GND
3
TOP VIEW
(Not to Scale)
6
GND
NC 4
5 EN/UVLO
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO
THIS PIN.
2. IT IS HIGHLY RECOMMENDED THAT THE
EXPOSED PAD ON THE BOTTOM OF THE
PACKAGE BE CONNECTED TO THE GROUND
PLANE ON THE BOARD.
Figure 4. Narrow Body SOIC Package
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
1 VOUT
2 SENSE/ADJ
3 GND
4 NC
5 EN/UVLO
6 GND
7 PG
8 VIN
EPAD
Description
Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor.
Sense (SENSE). Measures the actual output voltage at the load and feeds it to the error amplifier.
Connect SENSE as close as possible to the load to minimize the effect of IR drop between the
regulator output and the load. This function applies to fixed voltages only.
Adjust Input (ADJ). An external resistor divider sets the output voltage. This function applies to
adjustable voltages only.
Ground.
Do Not Connect to this Pin.
Enable Input (EN). Drive EN high to turn on the regulator; drive EN low to turn off the regulator.
For automatic startup, connect EN to VIN.
Programmable Undervoltage Lockout (UVLO). When the programmable UVLO function is used,
the upper and lower thresholds are determined by the programming resistors.
Ground.
Power Good. This open-drain output requires an external pull-up resistor to VIN or VOUT. If the
part is in shutdown, current limit, thermal shutdown, or falls below 90% of the nominal output
voltage, PG immediately transitions low. If the power-good function is not used, the pin may be
left open or connected to ground.
Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor.
Exposed Pad. Exposed paddle on the bottom of the package. The EPAD enhances thermal
performance and is electrically connected to GND inside the package. It is highly recommended
that the EPAD be connected to the ground plane on the board.
Rev. B | Page 6 of 28
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共有リンク

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