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D720112GK の電気的特性と機能

D720112GKのメーカーはNECです、この部品の機能は「UPD720112」です。


製品の詳細 ( Datasheet PDF )

部品番号 D720112GK
部品説明 UPD720112
メーカ NEC
ロゴ NEC ロゴ 




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D720112GK Datasheet, D720112GK PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD720112
USB 2.0 HUB CONTROLLER
The µPD720112 is a USB 2.0 hub device that complies with the Universal Serial Bus (USB) Specification Revision
2.0 and works up to 480 Mbps. USB 2.0 compliant transceivers are integrated for upstream and all downstream ports.
The µPD720112 works backward compatible either when any one of the downstream ports is connected to a USB 1.1
compliant device, or when the upstream port is connected to a USB 1.1 compliant host.
Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.
µPD720112 User’s Manual: S16617E
FEATURES
Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps)
Certified by USB implementers forum and granted the USB 2.0 high-speed Logo
High-speed or full-speed packet protocol sequencer for Endpoint 0/1
4 (Max.) downstream facing ports
All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5
Mbps) transaction.
Supports split transaction to handle full-speed and low-speed transaction on downstream facing ports when
Hub controller is working in high-speed mode.
One Transaction Translator per Hub and supports four non-periodic buffers
Supports self-powered and bus-powered mode
Supports Over-current detection and Individual or ganged power control
Supports configurable vendor ID, product ID, string descriptors and others with external Serial ROM
Supports “non-removable” attribution on individual port
Uses 30 MHz X’tal, or clock input
Supports downstream port status with LED
2.5 V and 3.3 V power supplies
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S16616EJ2V0DS00 (2nd edition)
Date Published September 2004 NS CP (N)
Printed in Japan
2004
Free Datasheet http://www.Datasheet4U.com

1 Page





D720112GK pdf, ピン配列
µPD720112
APLL
ALL_TT
CDR
DPC
DP(n)_PHY
EP0
EP1
F_TIM (Frame Timer)
FS_REP
OSB
ROM I/F
SERDES
SIE_2H
UP_PHY
UPC
: Generates all clocks of Hub.
: Translates the high-speed transactions (split transactions) for full/low-speed device
to full/low-speed transactions. ALL_TT buffers the data transfer from either
upstream or downstream direction. For OUT transaction, ALL_TT buffers data from
upstream port and sends it out to the downstream facing ports after speed
conversion from high-speed to full/low-speed. For IN transaction, ALL_TT buffers
data from downstream ports and sends it out to the upstream facing ports after
speed conversion from full/low-speed to high-speed.
: Data & clock recovery circuit
: Downstream Port Controller handles Port Reset, Enable, Disable, Suspend and
Resume
: Downstream transceiver supports high-speed (480 Mbps), full-speed (12 Mbps), and
low-speed (1.5 Mbps) transaction
: Endpoint 0 controller
: Endpoint 1 controller
: Manages hub’s synchronization by using micro-SOF which is received at upstream
port, and generates SOF packet when full/low-speed device is attached to
downstream facing port.
: Full/low-speed repeater is enabled when the µPD720112 are worked at full-speed
mode
: Oscillator Block
: Interface block for external Serial ROM which contains user-defined descriptors
: Serializer and Deserializer
: Serial Interface Engine (SIE) controls USB2.0 and 1.1 protocol sequencer.
: Upstream Transceiver supports high-speed (480 Mbps), full-speed (12 Mbps)
transaction
: Upstream Port Controller handles Suspend and Resume
Data Sheet S16616EJ2V0DS
3
Free Datasheet http://www.Datasheet4U.com


3Pages


D720112GK 電子部品, 半導体
µPD720112
1. PIN INFORMATION
Pin Name
X1_CLK
X2
SYSRSTB
RPU
DP(4:1)
DM(4:1)
DPU
DMU
BUS_SELF
LPWRM
RREF
CSB(4:1)
PPB(4:1)
VBUSM
SCL
SDA/GANG_B
EXROM_EN
AMBER
GREEN
LED(4:1)
TEST
SCAN_MODE
VDD33
VDD25
AVDD
VSS
AVSS
AVSS(R)
I/O Buffer Type
I
O
I
A (O)
I/O
I/O
I/O
I/O
I
I
A (O)
I
O
I
O
I/O
2.5 V input
2.5 V output
5 V tolerant Schmitt input
USB pull-up control
USB D+ signal I/O
USB Dsignal I/O
USB D+ signal I/O
USB Dsignal I/O
3.3 V Schmitt input
3.3 V Schmitt input
Analog
5 V tolerant input
5 V tolerant N-ch open drain
5 V tolerant Schmitt input
3.3 V output
3.3 V Schmitt I/O
I 3.3 V Schmitt input
O 5 V tolerant output
O 5 V tolerant output
O 5 V tolerant output
I 3.3 V input
I 3.3 V input
Active
Level
Low
Low
Low
Low
Function
Crystal oscillator in or clock input
Oscillator out
Asynchronous chip reset
External 1.5 kpull-up resistor control
USB’s downstream facing port D+ signal
USB’s downstream facing port Dsignal
USB’s upstream facing port D+ signal
USB’s upstream facing port Dsignal
Power mode select
Local power monitor
Reference resistor
Port’s over-current status input
Port’s power supply control output
VBUS monitor
External serial ROM clock out
External serial ROM data IO or power
management mode select
External serial ROM input enable
Amber colored LED control output
Green colored LED control output
LED indicator output for downstream port status
Test signal
Test signal
3.3 V VDD
2.5 V VDD
2.5 V VDD for analog circuit
VSS
VSS for analog circuit
VSS for reference resistor. Connect to AVSS.
Remark “5 V tolerant“ means that the buffer is 3 V buffer with 5 V tolerant circuit.
6 Data Sheet S16616EJ2V0DS
Free Datasheet http://www.Datasheet4U.com

6 Page



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部品番号部品説明メーカ
D720112GK

UPD720112

NEC
NEC


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