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K4B2G1646EのメーカーはSamsungです、この部品の機能は「2Gb E-die DDR3 SDRAM」です。 |
部品番号 | K4B2G1646E |
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部品説明 | 2Gb E-die DDR3 SDRAM | ||
メーカ | Samsung | ||
ロゴ | |||
このページの下部にプレビューとK4B2G1646Eダウンロード(pdfファイル)リンクがあります。 Total 65 pages
Rev. 1.21, Jun. 2012
K4B2G1646E
2Gb E-die DDR3 SDRAM Only x16
96FBGA with Lead-Free & Halogen-Free
(RoHS compliant)
datasheet
SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND
SPECIFICATIONS WITHOUT NOTICE.
Products and specifications discussed herein are for reference purposes only. All information discussed
herein is provided on an "AS IS" basis, without warranties of any kind.
This document and all information discussed herein remain the sole and exclusive property of Samsung
Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property
right is granted by one party to the other party under this document, by implication, estoppel or other-
wise.
Samsung products are not intended for use in life support, critical care, medical, safety equipment, or
similar applications where product failure could result in loss of life or personal or physical harm, or any
military or defense application, or any governmental procurement to which special terms or provisions
may apply.
For updates or additional information about Samsung products, contact your nearest Samsung office.
All brand names, trademarks and registered trademarks belong to their respective owners.
ⓒ 2012 Samsung Electronics Co., Ltd. All rights reserved.
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Free Datasheet http://www.Datasheet4U.com
1 Page K4B2G1646E
datasheet
Rev. 1.21
DDR3 SDRAM
Table Of Contents
2Gb E-die DDR3 SDRAM Only x16
1. Ordering Information ..................................................................................................................................................... 5
2. Key Features................................................................................................................................................................. 5
3. Package pinout/Mechanical Dimension & Addressing.................................................................................................. 6
3.1 x16 Package Pinout (Top view) : 96ball FBGA Package ........................................................................................ 6
3.2 FBGA Package Dimension (x16)............................................................................................................................. 7
4. Input/Output Functional Description.............................................................................................................................. 8
5. DDR3 SDRAM Addressing ........................................................................................................................................... 9
6. Absolute Maximum Ratings .......................................................................................................................................... 10
6.1 Absolute Maximum DC Ratings............................................................................................................................... 10
6.2 DRAM Component Operating Temperature Range ................................................................................................ 10
7. AC & DC Operating Conditions..................................................................................................................................... 10
7.1 Recommended DC operating Conditions (SSTL_1.5)............................................................................................. 10
8. AC & DC Input Measurement Levels ............................................................................................................................ 11
8.1 AC & DC Logic input levels for single-ended signals .............................................................................................. 11
8.2 VREF Tolerances...................................................................................................................................................... 12
8.3 AC & DC Logic Input Levels for Differential Signals............................................................................................... 13
8.3.1. Differential signals definition ............................................................................................................................ 13
8.3.2. Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS) .................................................. 13
8.3.3. Single-ended requirements for differential signals ........................................................................................... 14
8.4 Differential Input Cross Point Voltage...................................................................................................................... 15
8.5 Slew rate definition for Differential Input Signals ..................................................................................................... 15
8.6 Slew rate definitions for Differential Input Signals ................................................................................................... 15
9. AC & DC Output Measurement Levels ......................................................................................................................... 16
9.1 Single-ended AC & DC Output Levels..................................................................................................................... 16
9.2 Differential AC & DC Output Levels......................................................................................................................... 16
9.3 Single-ended Output Slew Rate .............................................................................................................................. 16
9.4 Differential Output Slew Rate .................................................................................................................................. 17
9.5 Reference Load for AC Timing and Output Slew Rate ............................................................................................ 17
9.6 Overshoot/Undershoot Specification ....................................................................................................................... 18
9.6.1. Address and Control Overshoot and Undershoot specifications...................................................................... 18
9.6.2. Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications ...................................................... 19
9.7 34ohm Output Driver DC Electrical Characteristics................................................................................................. 20
9.7.1. Output Drive Temperature and Voltage Sensitivity .......................................................................................... 21
9.8 On-Die Termination (ODT) Levels and I-V Characteristics ..................................................................................... 21
9.8.1. ODT DC Electrical Characteristics ................................................................................................................... 22
9.8.2. ODT Temperature and Voltage sensitivity ....................................................................................................... 23
9.9 ODT Timing Definitions ........................................................................................................................................... 24
9.9.1. Test Load for ODT Timings .............................................................................................................................. 24
9.9.2. ODT Timing Definitions .................................................................................................................................... 24
10. IDD Current Measure Method ..................................................................................................................................... 27
10.1 IDD Measurement Conditions ............................................................................................................................... 27
11. 2Gb DDR3 SDRAM E-die IDD Specification Table .................................................................................................... 36
12. Input/Output Capacitance ........................................................................................................................................... 37
13. Electrical Characteristics and AC timing for DDR3-800 to DDR3-2133 ...................................................................... 38
13.1 Clock Specification ................................................................................................................................................ 38
13.1.1. Definition for tCK(avg).................................................................................................................................... 38
13.1.2. Definition for tCK(abs).................................................................................................................................... 38
13.1.3. Definition for tCH(avg) and tCL(avg) .............................................................................................................. 38
13.1.4. Definition for note for tJIT(per), tJIT(per, Ick) ................................................................................................. 38
13.1.5. Definition for tJIT(cc), tJIT(cc, Ick) ................................................................................................................. 38
13.1.6. Definition for tERR(nper)................................................................................................................................ 38
13.2 Refresh Parameters by Device Density................................................................................................................. 39
13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ................................................................. 39
13.3.1. Speed Bin Table Notes .................................................................................................................................. 44
-3-
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3Pages K4B2G1646E
datasheet
3. Package pinout/Mechanical Dimension & Addressing
3.1 x16 Package Pinout (Top view) : 96ball FBGA Package
Rev. 1.21
DDR3 SDRAM
1
2
3 456 7
8
A
VDDQ
DQU5
DQU7
B VSSQ VDD
VSS
C
VDDQ
DQU3
DQU1
D
VSSQ
VDDQ
DMU
E
VSS
VSSQ
DQL0
F
VDDQ
DQL2
DQSL
G
VSSQ
DQL6
DQSL
H
VREFDQ
VDDQ
DQL4
J NC VSS RAS
K ODT VDD CAS
L NC CS WE
M VSS BA0 BA2
N VDD
A3
A0
P VSS
A5
A2
R VDD
A7
A9
T VSS RESET A13
DQU4
DQSU
DQSU
DQU0
DML
DQL1
VDD
DQL7
CK
CK
A10/AP
NC
A12/BC
A1
A11
NC
VDDQ
DQU6
DQU2
VSSQ
VSSQ
DQL3
VSS
DQL5
VSS
VDD
ZQ
VREFCA
BA1
A4
A6
A8
9
VSS
VSSQ
VDDQ
VDD
VDDQ
VSSQ
VSSQ
VDDQ
NC
CKE
NC
VSS
VDD
VSS
VDD
VSS
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Ball Locations (x16)
Populated ball
Ball not populated
Top view
(See the balls through the package)
123456789
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
-6-
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6 Page | |||
ページ | 合計 : 65 ページ | ||
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部品番号 | 部品説明 | メーカ |
K4B2G1646B | 2Gb B-die DDR3 SDRAM | Samsung |
K4B2G1646C | 2Gb C-die DDR3 SDRAM | Samsung semiconductor |
K4B2G1646E | 2Gb E-die DDR3 SDRAM | Samsung |
K4B2G1646F | 2Gb F-die DDR3L SDRAM x16 | Samsung |