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PDF AR6003 Data sheet ( Hoja de datos )
| Número de pieza | AR6003 | |
| Descripción | Single Chip 802.11n MAC/BB/Radio | |
| Fabricantes | Atheros | |
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Data Sheet
January 2010
AR6003 Single Chip 802.11n MAC/BB/Radio for Embedded
Applications
General Description
The Atheros AR6003 is a single chip, small form
factor IEEE 802.11 a/b/g/n MAC/baseband/
radio optimized for low-power mobile
applications. It is the 3rd generation WLAN
design in the ROCm® family, employing the
world's lowest power consumption WLAN
architecture in the smallest possible form factor.
The AR6003 is a single stream 1x1 802.11n
implementation providing improved link
robustness, extended range, increased
throughput and better performance for an
unparalleled user experience. The AR6003 is part
of the AlignTM product family.
The AR6003 family implements sophisticated
design techniques to deliver a solution which
will greatly extend the battery life of mobile and
embedded systems. It leverages its near-zero
power in idle and stand-by modes to enable
users to leave WLAN "always-on" without
impacting battery life.
The AR6003 family implements Atheros'
proprietary Internal Efficient Power AmplifierTM
(EPA) technology in CMOS with advanced
linearization algorithms and an internal LNA,
thereby reducing the BOM costs in the system
design. It provides the option for an additional
external PA for larger output power if needed.
The AR6003 has additional LDOs to provide
noise isolation for digital and analog supplies.
The AR6003 family supports 2-, 3-, and 4-wire
Bluetooth coexistence protocols with advanced
algorithms for predicting channel usage by a co-
located Bluetooth transceiver.
The AR6003 family provides multiple peripheral
interfaces including UART, SPI, I2C, etc., via 26
GPIO pins. The only external clock source
needed for AR6003-based designs is a high-speed
crystal or oscillator. A variety of reference clocks
are supported which include 19.2, 24, 26, 38.4, 40
and 52 MHz. AR6003 chips are available in Wafer
Level Chip Scale Packages (WLCSP) or Ball Grid
Arrays (BGA) packaging.
AR6003 Features
■ All-CMOS IEEE 802.11a/b/g/n or 802.11b/
g/n single-chip client
■ Single stream 802.11n provides highest
throughput and superior RF performance for
handhelds.
■ Advanced 1x1 802.11n features:
– 40MHz channels at 5GHz
– Full/Half Guard Interval
– Frame Aggregation
– Space Time Block Coding (STBC)
– Low Density Parity Check (LDPC)
Encoding
■ Integrated high-output Atheros Efficient
Power AmplifierTM and LNA for lowest
BOM.
■ Supports popular interfaces used in
embedded designs: SDIO v2.0 (50MHz, 4-bit
and 1-bit) and GSPI.
■ Lowest power consumption in the industry
with near zero in idle/standby modes,
extending battery life.
■ Integrated on-chip processor to minimize the
loading on host processor.
■ Supports 2/3/4-wire enhanced PTA scheme
for use with any BT solution for optimal
coexistence implementation.
■ Supports several reference clocks from
19.2MHz to 52MHz.
© 2010 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Atheros XR®, Driving the Wireless Future®, ROCm®, Super A/G®, Super G®,
Super N®, Total 802.11®, XSPAN®, Wireless Future. Unleashed Now.®, and Wake on Wireless® are registered by Atheros Communications, Inc. Atheros SST™, Signal-
Sustain Technology™, the Air is Cleaner at 5-GHz™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of Atheros
Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
•1
Free Datasheet http://www.Datasheet4U.com
1 page  
1. Functional Description
1.1 Overview
The AR6003 is a single chip 802.11 a/b/g/n
device based on cutting edge technology,
optimized for low power embedded
applications. The typical data path consists of
the host interface, mailbox DMA, AHB,
memory controller, MAC, BB, and radio. The
CPU drives the control path via register and
memory accesses. External interfaces include
SDIO or GSPI, reference clock, and front-end
components as well as optional connections
such as UART, SPI/I2C, GPIO, JTAG, 32 kHz
source. See the AR6003 block diagram.
1.2 XTENSA CPU
At the heart of the chip is the XTENSA CPU.
This CPU has four interfaces:
■ The Code RAM/ROM interface (iBus),
going to the Memory Controller (MC).
■ The Data RAM Interface (dBus), going to
the MC
■ The AHB interface, used mainly for register
accesses.
■ JTAG interface for debugging
1.3 Memory Controller (MC)
The MC contains 256 kBytes of ROM and 256
kBytes of RAM. It has three interfaces:
■ iBus,
■ dBus, and
■ AHB interface.
Any one of these interfaces can request access
to the ROM or RAM modules within the MC.
The MC contains arbiters to serve these three
interfaces on a first-come-first-serve basis.
1.4 AHB and APB Blocks
The AHB block acts as an arbiter. It has AHB
interfaces from three Masters:
■ MAC,
■ MBOX (from the Host), and
■ CPU.
See below for more on the MBOX and MAC.
Depending upon the address, the AHB data
request can go into one of the two slaves: APB
block or the MC. Data requests to the MC are
generally high-speed memory requests, while
requests to the APB block are primarily meant
for register access.
The APB block acts as a decoder. It is meant
only for access to programmable registers
within the AR6003’s main blocks. Depending
on the address, the APB request can go to one
of the places listed below:
■ Radio
■ MC
■ SI/SPI
■ MBOX
■ GPIO
■ UART
■ Real Time Clock (RTC), or
■ MAC/BB
1.5 Master SI/SPI Control
The AR6003 has a master serial interface (SI)
that can operate in two, three, or four-wire bus
configurations to control EEPROMs or other
I2C/SPI devices. Multiple I2C devices with
different device addresses are supported by
sharing the two-wire bus. Multiple SPI devices
are supported by sharing the clock and data
signals and using separate software-controlled
GPIO pins as chip selects.
An SI transaction consists of two phases: a data
transmit phase of 0-8 bytes followed by a data
receive phase of 0-8 bytes. The flexible SI
programming interface allows software to
support various address and command
configurations in I2C/SPI devices. In addition,
software may operate the SI in either polling or
interrupt mode.
1.6 GPIO
The AR6003 has 26 GPIO pins with direct
software access. Many are multiplexed with
other functions such as the host interface,
UART, SI, Bluetooth coexistence, etc. (see
Chapter 6 for details). Each GPIO supports the
following configurations via software
programming:
■ Internal pull-up/down options
■ Input available for sampling by a software
register
■ Input triggering an edge or level CPU
interrupt
Atheros Communications, Inc. AR6003 Single Chip 802.11n MAC/BB/Radio for Embedded Applications • 5
ATHEROS CONFIDENTIAL
January 2010 • 5
Free Datasheet http://www.Datasheet4U.com
5 Page 
2. Radio
The AR6003 transceiver consists of five major
functional blocks (see Figure 2-1):
■ Receiver (Rx)
■ Transmitter (Tx)
■ Frequency synthesizer (SYNTH)
■ Associated bias/control (BIAS)
■ Power Management Unit (PMU)
RFIn
Receiver
RxOut
Frequency
Synthesizer
RFCLK
RFOut
Transmitter
TxIn
Bias/Control
PMU
Radio
Control
Figure 2-1. Radio Functional Block Diagram
2.1 Receiver (Rx) Block
The receiver converts an RF signal (with 40
MHz bandwidth) to baseband I and Q outputs.
The receiver is tuned to 2.4 GHz and 5 GHz for
IEEE 802.11 b/g/n and 802.11a/n signals,
respectively. Figure 2-2 shows the Radio Tx/Rx
block diagram.
For 5 GHz operation, the receiver is comprised
of a low noise amplifier (LNA) followed by a
variable gain amplifier (VGA), a radio
frequency (RF) mixer, an intermediate
frequency (IF) mixer, and a baseband
programmable gain filter. This receiver is
implemented using the sliding IF topology.
For 2 GHz operation, the receiver is comprised
of an LNA, a direct conversion mixer, and a
baseband programmable gain filter. This
receiver is implemented using the direct
conversion topology.
For both 5 GHz and 2 GHz paths, mixers down
convert the signal to baseband in-phase (I) and
quadrature-phase (Q) signals. The I and Q
signals are low-pass filtered and amplified by
the baseband programmable gain filter
controlled by digital logic. The baseband I and
Q signals are sent to the ADC. The baseband
programmable gain filter is shared between the
2 GHz and 5 GHz paths.
The DC offset of the receive chain is reduced
using multiple digital to analog converters
(DACs) controlled by the MAC/baseband
block. Additionally, the receive chain can be
digitally powered down to conserve power.
AR6003 Single Chip 802.11n MAC/BB/Radio for Embedded Applications Atheros Communications, Inc. • 11
ATHEROS CONFIDENTIAL
January 2010 • 11
Free Datasheet http://www.Datasheet4U.com
11 Page | ||
| Páginas | Total 40 Páginas | |
| PDF Descargar | [ Datasheet AR6003.PDF ] | |
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