PDF 48LC4M32B2 Data sheet ( Hoja de datos )

Número de pieza	48LC4M32B2
Descripción	MT48LC4M32B2
Fabricantes	Micron
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SDR SDRAM MT48LC4M32B2 – 1 Meg x 32 x 4 Banks 128Mb: x32 SDRAM Features Features • PC100-compliant • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto precharge, includes concurrent auto precharge and auto refresh modes • Self refresh mode (not available on AT devices) • Auto refresh – 64ms, 4096-cycle refresh (commercial and industrial) – 16ms, 4096-cycle refresh (automotive) • LVTTL-compatible inputs and outputs • Single 3.3V ±0.3V power supply • Supports CAS latency (CL) of 1, 2, and 3 Options • Configuration – 4 Meg x 32 (1 Meg x 32 x 4 banks) • Package – OCPL1 – 86-pin TSOP II (400 mil) – 86-pin TSOP II (400 mil) Pb-free – 90-ball VFBGA (8mm x 13mm) – 90-ball VFBGA (8mm x 13mm) Pb- free • Timing (cycle time) – 6ns (166 MHz) – 6ns (166 MHz) – 7ns (143 MHz) • Revision • Operating temperature range – Commercial (0°C to +70°C) – Industrial (–40°C to +85°C) – Automotive (–40°C to +105°C) Marking 4M32B2 TG P F5 B5 -6A2 -63 -73 :G/:L None IT AT4 Notes: 1. Off-center parting line. 2. Available only on Revision L. 3. Available only on Revision G. 4. Contact Micron for availability. Table 1: Key Timing Parameters CL = CAS (READ) latency Clock Speed Grade Frequency (MHz) -6A 167 -6 167 -7 143 Target tRCD-tRP-CL 3-3-3 3-3-3 3-3-3 tRCD (ns) 18 18 20 tRP (ns) 18 18 20 CL (ns) 18 18 21 PDF: 09005aef80872800 128mb_x32_sdram.pdf - Rev. U 04/13 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2001 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. Free Datasheet http://www.Datasheet4U.com 1 page 128Mb: x32 SDRAM Features Figure 51: Clock Suspend Mode ..................................................................................................................... 79 PDF: 09005aef80872800 128mb_x32_sdram.pdf - Rev. U 04/13 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2001 Micron Technology, Inc. All rights reserved. Free Datasheet http://www.Datasheet4U.com 5 Page 128Mb: x32 SDRAM Pin and Ball Assignments and Descriptions Table 4: Pin/Ball Descriptions Symbol CLK CKE CS# CAS#, RAS#, WE# DQM[3:0] BA[1:0] A[11:0] DQ[31:0] NC VDDQ VSSQ VDD VSS Type Description Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides precharge power-down and SELF REFRESH operation (all banks idle), active power-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in pro- gress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, in- cluding CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Input Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command de- coder. All commands are masked when CS# is registered HIGH, but READ/WRITE bursts already in progress will continue, and DQM operation will retain its DQ mask capability while CS# is HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is consid- ered part of the command code. Input Command inputs: CAS#, RAS#, and WE# (along with CS#) define the command being en- tered. Input Input/output mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are High-Z (two-clock latency) during a READ cycle. DQM0 corresponds to DQ[7:0], DQM1 corresponds to DQ[15:8], DQM2 corresponds to DQ[23:16], and DQM3 corre- sponds to DQ[31:24]. DQM[3:0] are considered the same state when referenced as DQM. Input Bank address inputs: BA[1:0] define to which bank the ACTIVE, READ, WRITE, or PRE- CHARGE command is being applied. Input Address inputs: A[11:0] are sampled during the ACTIVE command (row address A[10:0]) and READ or WRITE command (column address A[7:0] with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRE- CHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selec- ted by BA[1:0] (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Input/ Data input/output: Data bus. Output – No connect: These pins should be left unconnected. Pin 70 is reserved for SSTL reference voltage supply. Supply DQ power supply: Isolated on the die for improved noise immunity. Supply DQ ground: Provides isolated ground to DQs for improved noise immunity. Supply Power supply: 3.3V ±0.3V. Supply Ground. PDF: 09005aef80872800 128mb_x32_sdram.pdf - Rev. U 04/13 EN 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2001 Micron Technology, Inc. All rights reserved. Free Datasheet http://www.Datasheet4U.com 11 Page

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