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A25L512 の電気的特性と機能

A25L512のメーカーはAMICです、この部品の機能は「(A25L010 - A25L512) Serial Flash Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 A25L512
部品説明 (A25L010 - A25L512) Serial Flash Memory
メーカ AMIC
ロゴ AMIC ロゴ 




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A25L512 Datasheet, A25L512 PDF,ピン配置, 機能
A25L020/A25L010/A25L512 Series
2Mbit / 1Mbit / 512Kbit Low Voltage, Serial Flash Memory
With 100MHz Uniform 4KB Sectors
Document Title
2Mbit /1Mbit /512Kbit, Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB
Sectors
Revision History
Rev. No.
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
History
Initial issue
Add 8-pin TSSOP package type
Add the spec. of ICC3 for 33MHz
Modify DC/AC Characteristics
Modify AC Characteristics
Add packing description in Part Numbering Scheme
P30: Change Data Retention and Endurance value from Max.
to Min.
P37: Add A25L512V-UF, A25L010V-UF and A25L020V-UF
in the ordering information
Add 8-pin USON (2*3mm) package type
P33: Modify the fR to 66MHz (Max.)
Add 8-pin WSON (6*5mm) package type
P31 : Add the typical ICC3 @ 100Mhz / 50Mhz / 33Mhz
Add typical ICC4
P28, 29 : Update power-up and power-down timing waveform
P31: Modify DC Characteristics
Issue Date
February 27, 2008
September 2, 2008
January 9, 2009
April 21, 2009
April 30, 2010
October 20, 2010
December 23, 2010
January 31, 2011
October 28, 2011
March 30, 2012
May 9, 2012
Remark
Final
(May, 2012, Version 2.0)
AMIC Technology Corp.
Free Datasheet http://www.Datasheet4U.com

1 Page





A25L512 pdf, ピン配列
Pin Configurations (Continued)
„ TSSOP8 Connections
A25L010/
A25L512
S1
DO 2
W3
VSS 4
8 VCC
7 HOLD
6C
5 DIO
A25L020/A25L010/A25L512 Series
„ USON8/WSON8 Connections
A25L020/
A25L010/
A25L512
S1
DO 2
W3
VSS 4
8 VCC
7 HOLD
6C
5 DIO
Block Diagram
HOLD
W
S
C
DIO
DO
Control Logic
Address register
and Counter
High Voltage
Generator
I/O Shift Register
256 Byte
Data Buffer
3FFFFh (2M),
1FFFFh (1M)
FFFFh (512K)
Status
Register
Size of the
memory area
00000h
000FFh
256 Byte (Page Size)
X Decoder
(May, 2012, Version 2.0)
2 AMIC Technology Corp.
Free Datasheet http://www.Datasheet4U.com


3Pages


A25L512 電子部品, 半導体
OPERATING FEATURES
Page Programming
To program one data byte, two instructions are required: Write
Enable (WREN), which is one byte, and a Page Program (PP)
sequence, which consists of four bytes plus data. This is
followed by the internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP) instruction
allows up to 256 bytes to be programmed at a time (changing
bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
Sector Erase, Block Erase, and Chip Erase
The Page Program (PP) instruction allows bits to be reset
from 1 to 0. Before this can be applied, the bytes of memory
need to have been erased to all 1s (FFh). This can be
achieved, a sector at a time, using the Sector Erase (SE)
instruction, a block at a time, using the Block Erase (BE)
instruction, or throughout the entire memory, using the Chip
Erase (CE) instruction. This starts an internal Erase cycle (of
duration tSE, tBE, or tCE).
The Erase instruction must be preceded by a Write Enable
(WREN) instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register
(WRSR), Program (PP) or Erase (SE, BE, or CE) can be
achieved by not waiting for the worst case delay (tW, tPP, tSE,
tBE, tCE). The Write In Progress (WIP) bit is provided in the
Status Register so that the application program can monitor
its value, polling it to establish when the previous Write cycle,
Program cycle or Erase cycle is complete.
Active Power, Stand-by Power and Deep
Power-Down Modes
When Chip Select ( S ) is Low, the device is enabled, and in
the Active Power mode.
When Chip Select ( S ) is High, the device is disabled, but
could remain in the Active Power mode until all internal cycles
have completed (Program, Erase, Write Status Register). The
device then goes in to the Stand-by Power mode. The device
consumption drops to ICC1.
The Deep Power-down mode is entered when the specific
instruction (the Deep Power-down Mode (DP) instruction) is
executed. The device consumption drops further to ICC2. The
device remains in this mode until another specific instruction
(the Release from Deep Power-down Mode and Read
Electronic Signature (RES) instruction) is executed.
All other instructions are ignored while the device is in the
Deep Power-down mode. This can be used as an extra
software protection mechanism, when the device is not in
active use, to protect the device from inadvertent Write,
Program or Erase instructions.
A25L020/A25L010/A25L512 Series
Status Register
The Status Register contains a number of status and control
bits that can be read or set (as appropriate) by specific
instructions.
WIP bit. The Write In Progress (WIP) bit indicates whether
the memory is busy with a Write Status Register, Program or
Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indicates the
status of the internal Write Enable Latch.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits
are non-volatile. They define the size of the area to be
software protected against Program and Erase instructions.
SRWD bit. The Status Register Write Disable (SRWD) bit is
operated in conjunction with the Write Protect ( W ) signal.
The Status Register Write Disable (SRWD) bit and Write
Protect ( W ) signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bits of the
Status Register (SRWD, BP2, BP1, BP0) become read-only
bits.
Protection Modes
The environments where non-volatile memory devices are
used can be very noisy. No SPI device can operate correctly
in the presence of excessive noise. To help combat this, the
A25L020/A25L010/A25L512 boasts the following data
protection mechanisms:
„ Power-On Reset and an internal timer (tPUW) can provide
protection against inadvertent changes while the power
supply is outside the operating specification.
„ Program, Erase and Write Status Register instructions are
checked that they consist of a number of clock pulses that
is a multiple of eight, before they are accepted for
execution.
„ All instructions that modify data must be preceded by a
Write Enable (WREN) instruction to set the Write Enable
Latch (WEL) bit. This bit is returned to its reset state by
the following events:
- Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
„ The Block Protect (BP2, BP1, BP0) bits allow part of the
memory to be configured as read-only. This is the
Software Protected Mode (SPM).
„ The Write Protect ( W ) signal allows the Block Protect
(BP2, BP1, BP0) bits and Status Register Write Disable
(SRWD) bit to be protected. This is the Hardware
Protected Mode (HPM).
„ In addition to the low power consumption feature, the
Deep Power-down mode offers extra software protection
from inadvertent Write, Program and Erase instructions,
as all instructions are ignored except one particular
instruction (the Release from Deep Power-down
instruction).
(May, 2012, Version 2.0)
5 AMIC Technology Corp.
Free Datasheet http://www.Datasheet4U.com

6 Page



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共有リンク

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部品番号部品説明メーカ
A25L512

(A25L010 - A25L512) Serial Flash Memory

AMIC
AMIC
A25L512A

Serial Flash Memory

AMIC
AMIC


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