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Datasheet MC74HC11A PDF ( 特性, スペック, ピン接続図 )

部品番号 MC74HC11A
部品説明 Triple 3-Input AND Gate
メーカ Motorola
ロゴ Motorola ロゴ 
プレビュー
Total 5 pages
		
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MC74HC11A Datasheet, MC74HC11A PDF,ピン配置, 機能
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
Triple 3-Input AND Gate
High–Performance Silicon–Gate CMOS
The MC74HC11A is identical in pinout to the LS11. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 µA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 60 FETs or 15 Equivalent Gates
LOGIC DIAGRAM
A1
B1
1
2
13
C1
A2
B2
3
4
5
C2
A3
B3
9
10
11
C3
PIN 14 = VCC
PIN 7 = GND
12 Y1
6 Y2
8 Y3
Y = ABC
MC74HC11A
14
1
14
1
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
1
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
ORDERING INFORMATION
MC74HCXXAN
MC74HCXXAD
MC74HCXXADT
Plastic
SOIC
TSSOP
PIN ASSIGNMENT
A1 1
B1 2
A2 3
B2 4
C2 5
Y2 6
GND 7
14 VCC
13 C1
12 Y1
11 C3
10 B3
9 A3
8 Y3
FUNCTION TABLE
Inputs
Output
ABCY
LXXL
XLXL
XXL L
HHHH
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
12/97
© Motorola, Inc. 1997
1
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MC74HC11A pdf, ピン配列
MC74HC11A
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎDC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎGuaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
Parameter
Test Conditions
VCC
V
– 55 to
25_ C
v v85_C
125_ C Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVOL
Maximum Low–Level Output
Voltage
vVin = VIH
|Iout| 20 µA
2.0 0.1 0.1 0.1 V
4.5 0.1 0.1 0.1
6.0 0.1 0.1 0.1
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎvVin = VIH or VIL |Iout| 2.4 mA 3.0
0.26
0.33
0.40
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎv|Iout| 4.0mA 4.5
0.26
0.33
0.40
v|Iout| 5.2 mA 6.0
0.26
0.33
0.40
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎIin Maximum Input Leakage Current Vin = VCC or GND
6.0 ± 0.1 ± 1.0 ± 1.0 µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎICC MaximumQuiescent Supply
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCurrent (per Package)
Vin = VCC or GND
Iout = 0 µA
6.0 1
10 40 µA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎAC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎSymbol
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPLH,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtPHL
Parameter
Maximum Propagation Delay, Input A, B, or C to Output Y
(Figures 1 and 2)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎtTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎNOTES:
Maximum Input Capacitance
VCC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
– 55 to
25_ C
v 85_C v 125_C
95 120 145
45 60 75
19 24 29
16 20 25
75 95 110
30 40 55
15 19 22
13 16 19
10 10 10
Unit
ns
ns
pF
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Typical @ 25°C, VCC = 5.0 V
CPD
Power Dissipation Capacitance (Per Gate)*
27 pF
* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola High–Speed CMOS Data Book (DL129/D).
INPUT
A, B, OR C
OUTPUT Y
tr
90%
50%
10%
90%
50%
10%
tPLH
tTLH
tf
VCC
GND
tPHL
tTHL
Figure 1. Switching Waveforms
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 2. Test Circuit
A
BY
EXPANDED LOGIC DIAGRAM
C (1/3 OF THE DEVICE)
High–Speed CMOS Logic Data
DL129 — Rev 6
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