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PDF IS67WVE2M16DBLL Data sheet ( Hoja de datos )
| Número de pieza | IS67WVE2M16DBLL | |
| Descripción | (IS66WVE2M16DBLL / IS67WVE2M16DBLL) 3.0V Core Async/Page PSRAM | |
| Fabricantes | ISSI | |
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IS66WVE2M16DBLL
IS67WVE2M16DBLL
3.0V Core Async/Page PSRAM
Overview
The IS66WVE2M16DBLL and IS67WVE2M16DBLL is an integrated memory device containing 32Mbit
Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 2M words by 16 bits.
The device includes several power saving modes : Partial Array Refresh mode where data is retained in a
portion of the array and Deep Power Down mode. Both these modes reduce standby current drain. The
die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from
the device core.
Features
Asynchronous and page mode interface
Dual voltage rails for optional performance
VDD 2.7V~3.6V, VDDQ 2.7V~3.6V
Page mode read access
Interpage Read access : 70ns
Intrapage Read access : 20ns
Low Power Consumption
Asynchronous Operation < 30 mA
Intrapage Read < 18mA
Standby < 150 uA (max.)
Deep power-down (DPD) < 3uA (Typ)
Low Power Feature
Temperature Controlled Refresh
Partial Array Refresh
Deep power-down (DPD) mode
Operating temperature Range
Industrial: -40°C~85°C
Automotive A1: -40°C~85°C
Package:
48-ball TFBGA
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev. D | Oct. 2013
www.issi.com - [email protected]
1
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1 page  
IS66WVE2M16DBLL
IS67WVE2M16DBLL
Functional Description
All functions for the device are listed below in Table 2.
Table 2. Functional Descriptions
Mode
Standby
Read
Write
No operation
PAR
DPD
Load
Configuration
register
Power
Standby
Active
Active
Idle
PAR
DPD
Active
CE# WE# OE# UB#/LB# ZZ#
H XX X H
L HL L H
L LX L H
L XX X H
H XX X L
H XX X L
L LX X L
DQ
[15:0]4
High-Z
Data-Out
Data-In
X
High-Z
High-Z
High-Z
Note
2,5
1,4
1,3,4
4,5
6
6
Notes
1. When UB# and LB# are in select mode (LOW), DQ0~DQ15 are affected as shown.
When only LB# is in select mode, DQ0~DQ7 are affected as shown. When only UB# is
in select mode, DQ8~DQ15 are affected as shown.
2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data
inputs/outputs are internally isolated from any external influence.
3. When WE# is active, the OE# input is internally disabled and has no effect on the I/Os.
4. The device will consume active power in this mode whenever addresses are changed.
5. Vin=VDDQ or 0V, all device pins be static (unswitched) in order to achieve standby current.
6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.
Rev. D | Oct. 2013
www.issi.com - [email protected]
5
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5 Page 
IS66WVE2M16DBLL
IS67WVE2M16DBLL
Partial-Array Refresh
Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory
array. This feature enables the device to reduce standby current by refreshing only that
part of the memory array that is absolutely necessary. The refresh options are full array,
and none of the array. Data stored in addresses not receiving refresh will become
corrupted. Read and WRITE operations are ignored during PAR operation.
The device only enters PAR mode if the sleep bit in the CR has been set HIGH (CR[4] = 1).
PAR can be initiated by taking the ZZ# ball to the LOW state for longer than 10us.
Returning ZZ# to HIGH will cause an exit from PAR, and the entire array will be immediately
available for READ and WRITE operations.
Alternatively, PAR can be initiated using the CR software-access sequence (see “Software
Access to the Configuration Register”). Using this method, PAR is enabled
immediately upon setting CR[4] to “1” However, using software access to write to the CR
alters the function of ZZ# so that ZZ# LOW no longer initiates PAR, even though ZZ#
continues to enable WRITEs to the CR. This functional change persists until the next
time the device is powered up.
Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode is
used if the system does not require the storage provided by the PSRAM device. Any
stored data will become corrupted upon entering DPD. When refresh activity has been
re-enabled, the PSRAM device will require 150μs to perform an initialization procedure
before normal operations can resume. READ and WRITE operations are ignored during
DPD operation.
The device can only enter DPD if the sleep bit in the CR has been set LOW (CR[4] =0).
DPD is initiated by bringing ZZ# to the LOW state for longer than 10us. Returning ZZ# to
HIGH will cause the device to exit DPD and begin a 150us initialization process. During
this time, the current consumption will be higher than the specified standby levels, but
considerably lower than the active current specification.
Driving ZZ# LOW puts the device in PAR mode if the SLEEP bit in the CR has been set
HIGH (CR[4] = 1).
The device should not be put into DPD using the CR software-access sequence.
Rev. D | Oct. 2013
www.issi.com - [email protected]
11
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