DataSheet.jp

IS66WVE2M16DBLL の電気的特性と機能

IS66WVE2M16DBLLのメーカーはISSIです、この部品の機能は「(IS66WVE2M16DBLL / IS67WVE2M16DBLL) 3.0V Core Async/Page PSRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS66WVE2M16DBLL
部品説明 (IS66WVE2M16DBLL / IS67WVE2M16DBLL) 3.0V Core Async/Page PSRAM
メーカ ISSI
ロゴ ISSI ロゴ 




このページの下部にプレビューとIS66WVE2M16DBLLダウンロード(pdfファイル)リンクがあります。

Total 28 pages

No Preview Available !

IS66WVE2M16DBLL Datasheet, IS66WVE2M16DBLL PDF,ピン配置, 機能
IS66WVE2M16DBLL
IS67WVE2M16DBLL
3.0V Core Async/Page PSRAM
Overview
The IS66WVE2M16DBLL and IS67WVE2M16DBLL is an integrated memory device containing 32Mbit
Pseudo Static Random Access Memory using a self-refresh DRAM array organized as 2M words by 16 bits.
The device includes several power saving modes : Partial Array Refresh mode where data is retained in a
portion of the array and Deep Power Down mode. Both these modes reduce standby current drain. The
die has separate power rails, VDDQ and VSSQ for the I/O to be run from a separate power supply from
the device core.
Features
Asynchronous and page mode interface
Dual voltage rails for optional performance
VDD 2.7V~3.6V, VDDQ 2.7V~3.6V
Page mode read access
Interpage Read access : 70ns
Intrapage Read access : 20ns
Low Power Consumption
Asynchronous Operation < 30 mA
Intrapage Read < 18mA
Standby < 150 uA (max.)
Deep power-down (DPD) < 3uA (Typ)
Low Power Feature
Temperature Controlled Refresh
Partial Array Refresh
Deep power-down (DPD) mode
Operating temperature Range
Industrial: -40°C~85°C
Automotive A1: -40°C~85°C
Package:
48-ball TFBGA
Copyright © 2013 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its
products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services
described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information
and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or
effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to
its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Rev. D | Oct. 2013
www.issi.com - [email protected]
1
Free Datasheet http://www.Datasheet4U.com

1 Page





IS66WVE2M16DBLL pdf, ピン配列
IS66WVE2M16DBLL
IS67WVE2M16DBLL
48Ball TFBGA Ball Assignment
1 23 456
A
LB# OE#
A0
A1 A2 ZZ#
B
DQ8 UB#
A3
A4 CE# DQ0
C
DQ9 DQ10
A5
A6 DQ1 DQ2
D
VSSQ DQ11 A17
A7 DQ3 VDD
E
VDDQ DQ12
NC
A16 DQ4 VSS
F
DQ14 DQ13 A14
A15 DQ5 DQ6
G
DQ15 A19
A12
A13 WE# DQ7
H A18 A8 A9 A10 A11 A20
[Top View]
(Ball Down)
Rev. D | Oct. 2013
www.issi.com - [email protected]
3
Free Datasheet http://www.Datasheet4U.com


3Pages


IS66WVE2M16DBLL 電子部品, 半導体
IS66WVE2M16DBLL
IS67WVE2M16DBLL
Functional Description
In general, this device is high-density alternatives to SRAM and Pseudo SRAM products popular
in low-power, portable applications.
The 32Mb device contains a 33,554,432-bit DRAM core organized as 2,097,152 addresses by
16 bits. This device include the industry-standard, asynchronous memory interface found on
other low-power SRAM or PSRAM offerings
Page mode access is also supported as a bandwidth-enhancing extension to the asynchronous
read protocol.
Power-Up Initialization
PSRAM products include an on-chip voltage sensor that is used to launch the power-up
initialization process. Initialization will load the CR with its default settings (see Table 3).
VDD and VDDQ must be applied simultaneously. When they reach a stable level above
2.7V, the device will require 150μs to complete its self-initialization process ( see Figure 1).
During the initialization period, CE# should remain HIGH. When initialization is complete,
the device is ready for normal operation.
Figure 1: Power-Up Initialization Timing
VDD=2.7V
VDD
VDDQ
tPU > 150us
Device Initialization
Device ready for
normal operation
Rev. D | Oct. 2013
www.issi.com - [email protected]
6
Free Datasheet http://www.Datasheet4U.com

6 Page



ページ 合計 : 28 ページ
 
PDF
ダウンロード
[ IS66WVE2M16DBLL データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
IS66WVE2M16DBLL

3.0V Core Async/Page PSRAM

ISSI
ISSI
IS66WVE2M16DBLL

(IS66WVE2M16DBLL / IS67WVE2M16DBLL) 3.0V Core Async/Page PSRAM

ISSI
ISSI


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap