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PDF AN-243 Data sheet ( Hoja de datos )
| Número de pieza | AN-243 | |
| Descripción | Graphics/Alphanumerics Systems Using the DP8350 | |
| Fabricantes | National Semiconductor | |
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Graphics Alphanumerics
Systems Using the DP8350
National Semiconductor
Application Note 243
Mike Evans
July 1986
This Application Note summarizes some CRT terminal cir-
cuits each with an increasing degree of graphics capability
and then goes into detail to describe a system having full
graphics capability with all dots individually programmable
All these applications use the DP8350 CRT Controller
Here are some of the features of the full graphics system
Hardware Features
The hardware is designed for a 24 row by 80 column
display with 7 dots per column and 10 lines per row
All ICs are made by National Semiconductor
Low I C cost all parts readily available
Fits on one standard BLC80 (SBC80) card
System performance only limited by software
8080 Mnemonics usable with STARPLEXTM or Intel-
lec Development Systems
All graphics programs very fast
Example One dot takes 500 ms maximum to plot
During display time each 7-dot cycle may be shared by
the microprocessor
8-bit word comprises MSB as attribute and next 7 bits as
7 dot word of a character line
Can input display data serially or parallel
Can output display data serially or parallel
Baud rate programmable from 110 to 56k baud
Can be used as slave to main system
Can copy characters from alphanumeric ROM or symbol
EPROM
13 kbytes of RAM available for user software or back-up
display storage
Analog inputs joystick or waveforms
Easily expandable to color graphics
Software Features
The software is programmed for any display configura-
tion of rows columns dots per column and lines per row
The hardware is designed for a 24 row by 80 column
display with 7 dots per column and 10 lines per row
Can perform most dumb terminal functions including
scrolling
Simultaneous display of alphanumerics and graphics
Identical terminals can display same information with in-
puts from either
Can save displays in computer storage
Can load displays from computer storage
Can erase any part of display or all of it
Can draw a rectangle linking any 2 horizontal and 2 verti-
cal coordinates
Can transfer in 1 10th second max any area of display to
any other area or to from backup display storage
Smooth movement of subject in any direction
Immediate display of fixed diagrams
In-system emulation of programs available
The DP8350 CRT Controller provides incrementing video
addresses starting from the Top of Page address or from a
new Row Start address These addresses and the Cursor
address are loaded into their respective registers from the
address bus All video control signals are provided by the
8350 so that apart from the crystal oscillator no extra video
circuitry is required
The DP8350 has so far been considered to be useable only
in dumb terminals whereas in fact it is easy to adapt it to
more complex terminals with full graphics capability Follow-
ing is a summary of the functions of the various combina-
tions of alphanumerics graphics displays beginning with a
dumb terminal using a monitor with 24 x 80 characters
Dumb Terminal
The basic dumb terminal design is shown in Figure 1 Usual-
ly the microprocessor loads the Character Position RAM (or
Refresh RAM) only during horizontal or vertical blanking or
during the last 3 lines of a row The CRTC then sequentially
addresses this RAM during display time The ASCII data
from this RAM (for the character selected) is outputted to
the ROM of the Character Generator The 7-dot word of this
character for the line being displayed is then loaded into a
shift register and shifted out as video to the monitor during
the next 7-dot cycle
The logical choice of CRT Controller for this simple CRT
terminal is the DP8350 The most common application is for
a 24 row by 80 column display with the character field com-
prised of 10 lines each of 7 dots The character itself occu-
pies 7 lines each of 5 dots leaving 3 lines for vertical char-
acter spacing and 2 dots for horizontal character spacing
Refer to AN-198 and AN-199 for further information on al-
phanumeric applications of CRTs
STARPLEXTM is a trademark of National Semiconductor Corp
Intellec is a registered trademark of Intel Corp
C1995 National Semiconductor Corporation TL F 5868
RRD-B30M105 Printed in U S A
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1 page  
Full Graphics Capability
We need to be able to select any dot on the display for full
graphics capability while still using the CRT controller to
sequence every line of every row as it does in the simple
terminal (See Figure 5 )
With the standard 24 x 80 character display full graphics
can be achieved by using a 24 (rows) by 80 (columns) by 10
(lines) address RAM and selecting the 7 dots as the data
word for the character position on the display and the line of
that character position
This means that alphanumeric characters can be displayed
in exactly the same format as with a simple terminal by
copying the character from ROM or EPROM into the select-
ed 10 line by 7-dot field line by line
Full graphics capability is also easily implemented once the
relevant software algorithms have been determined
So for full graphics every dot is one bit of memory There is
no refresh RAM refer to Figure 6 The CRTC scans through
the Display RAM a line at a time for each row on the CRT
causing the RAM outputs to be read every 7-dot cycle The
RAM output is shifted out two dot cycles later The micro-
processor may write into the Display RAM each 7-dot word
with ‘‘1’s’’ representing dots
Dot is at Line L Dot d character position is at Row r Column c
FIGURE 5 Full Graphics Capability Requires Individual Dot Selection
TL F 5868 – 5
FIGURE 6 Full Graphics System
5
TL F 5868 – 6
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Figure 12 shows the Memory Control Logic required to cor-
rectly sequence the control signals and busses to the dy-
namic RAMs and associated components The interfacing
from the 8080 microprocessor (via signals MEMR and
MEMW) is such that whenever the mP requests to read or
write to the dynamic RAMS the mP Access Flip-flops ac-
cess the RAMs at the start of the next mP cycle At the end
of these four dots the information has either been latched
into an 8-bit latch (for READ) or written into the RAMS (for
WRITE) The READY signal goes active at this time which
ensures that valid information is read at the end of the mP
cycle refer to Figure 10 Also the fact that MEMR and
MEMW occur at fixed intervals relative to the dot cycle sig-
nal LCGA means that system contention cannot occur
Therefore there is no need for arbitration between these
two signals when a microprocessor cycle is requested
This also applies when selecting the 8350 to change Top of
Page Row Start and Cursor To select any of these 3 regis-
ters the mP data bus bits D0 and D1 are connected to RA
and RB to select the required register
The information to be latched into the selected register has
to be valid on the CRTC address bus Because this is time
shared with the 8350 address counter which outputs the
incrementing display addresses during the second half of
every 7-dot cycle the CRTC register information has to be
valid for the first half of the next dot cycle The CRTC is
selected with DS6 7 and MEMW so that REGISTER LOAD
occurs just after the CRTC register information becomes
valid on the CRTC address bus The 8350 spec requires
that the address be valid 250 ns before REGISTER LOAD
trailing edge (old data sheets do not state this) and that RA
and RB are valid at the leading edge Note that the 8350
internal address counter can be enabled or disabled within
30 ns of the ADDRESS ENABLE changing state
All the Logic for Memory Control is Schottky due to the very
fast timing required in the system Note that the cycle time
of the CRTC half-cycle is 270 ns which is less than the 320
ns specified for the MM5290-2 This parameter is specified
at 320 ns for power dissipation reasons and because the
mP is not fast enough to use its half-cycle every 7-dot cycle
or 641 ns the average cycle time is greater than 320 ns
System Configuration
Figures 13 and 14 together show the system block diagram
The peripheral components of Figure 13 are used with the
microprocessor circuitry of Figure 14 The right hand half of
Figure 14 is equivlent to the circuitry of Figure 12
The LS138 address decoder is used for both I O and mem-
ory addressing Referring to Figure 15 address map the
peripherals are designated as I O and the EPROMs ROM
CRTC and dynamic RAMs as memory With address bit A15
HI the 32k dynamic RAM block is selected With address
bits A14 and A15 LO the LS138 outputs are selected A11
A12 and A13 are decoded to select which one of the LS138
outputs goes LO so that when memory is addressed each
section is 2 kbytes This includes the CRTC which requires
4 kbytes from 3000H to 3FFFH for 2 pages The top four
address bits select the CRTC and the remaining 12 address
bits are latched into the selected register
When addressing I O address bits A0–A7 also appear re-
spectively on A8 to 15 so that with A6 and A7 LO i e I O
address 00H to 3FH each LS138 output is now 8 bytes
selected by A3 A4 and A5 Bits A0 A1 and A2 are then
connected as required to the peripherals to select the ad-
dressed byte
PERIPHERALS
I O Port
In 00H or OUT 00H select the 8-bit parallel I O port which
basically is two octal latches with TRI-STATE outputs The 8
output bits may be connected to a master 8-bit data bus
When an external 8-bit data word is latched into the input
octal latch an interrupt causes this to be enabled on the mP
data bus when acknowledged with the instruction IN 00H
To output to the master databus OUT 00H causes the mP
data to be latched into the output latch and this also pro-
vides an external interrupt to the master system The master
can then read this data by enabling the output octal latch
Data can be transferred fast because the I O port normally
has the highest priority interrupt (IR 3 of the 8259) when
required
Interrupt Controller INS8250
This was also mentioned in an earlier section At initializa-
tion it is set up to remain in the fully nested mode so that
only higher priority interrups may interrupt an existing inter-
rupt Otherwise a lower priority interrupt has to wait for the
higher one to finish Normally the horizontal sync interrupt to
IR2 is masked off if there is no need to change ROW
START or soft scroll display data off the screen line by line
The I O address to select the 8259 can be either 10H or
11H refer to the 82569 data sheet and the software to de-
termine whether A0 is ‘0’ or ‘1’ Each interrupt routine has to
end with a SET END OF INTERRUPT instruction
Keyboard
The instruction IN 18H reads ASCII data on the keyboard
after a keyboard interrupt has been acknowledged
Serial I O Using the ACE INS8250
The 8250 with its associated EIA RS 232 interface allows
serial data to be received or transmitted 8 bits at a time with
the instructions IN 20H or OUT 20H The baud rate is previ-
ously determined as described in the software section Oth-
er ACE registers may be accessed by connecting A0 A1
and A2 of the mP address bus to the same designations on
ACE so that ACE addresses are from 20H to 26H During
block transfers such as dumping a picture on the screen
into an external memory or loading from the memory the
higher priority inputs can be masked off for fast transfers
Baud Rate Switch
See ‘Baud Rate’ for application the instruction OUT 28H
will read the 4 switch positions
A D Converter ADC0808
This 8 analog channel 8-bit A D converter has first to be
initialized to commence a conversion on one of the chan-
nels Address bits A0 A1 and A2 are used to select the
channel so that instruction OUT 3 nH starts a conversion
on INPUT n The conversion takes about 100 ms with the
780 kHz clock so the mP can continue operating during
conversion The END OF CONVERSION signal then inter-
rupts the mP which when acknowledged reads the 8-bit
data with the instruction IN 3 nH although n is not important
in reading the A D
The A D converter being only one 28-pin chip is ideal for
demonstrating the graphics capabilities of the system For
instance an x-y joystick can be connected to INPUT 0 and
INPUT 1 so that the movement of the joystick draws on the
screen
11
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