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74VHC165 の電気的特性と機能

74VHC165のメーカーはToshiba Semiconductorです、この部品の機能は「8-BIT SHIFT REGISTER」です。


製品の詳細 ( Datasheet PDF )

部品番号 74VHC165
部品説明 8-BIT SHIFT REGISTER
メーカ Toshiba Semiconductor
ロゴ Toshiba Semiconductor ロゴ 




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74VHC165 Datasheet, 74VHC165 PDF,ピン配置, 機能
TC74VHC165F/FT/FK
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC165F, TC74VHC165FT, TC74VHC165FK
8-Bit Shift Register (P-IN, S-OUT)
The TC74VHC165 is an advanced high speed CMOS 8-BIT
PARALLEL/SERIAL-IN, SERIAL-OUT SHIFT REGISTER
fabricated with silicon gate C2MOS technology.
It achieves the high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissipation.
It consists of parallel-in or serial-in, serial-out 8-bit shift register
with a gated clock input. When the SHIFT/ LOAD input is held
high, the serial data input is enabled and the eight frip-frops
perform serial shifting with each clock pulse.
When the SHIFT/ LOAD input is held low, the parallel data is
loaded synchronously into the register at positive going transition of
the clock pulse.
The CK-INH input should be shifted high only when the CK input
is held high.
An Input protection circuit ensures that 0 to 5.5 V can be applied
to the input pins without regard to the supply voltage. This device
can be used to interface 5 V to 3 V systems and on two supply
systems such as battery back up. This circuit prevents device
destruction due to mismatched supply and input voltages.
Features
High speed: fmax = 150 MHz (typ.) at VCC = 5 V
Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
High noise immunity: VNIH = VNIL = 28% VCC (min)
Power down protection is provided on all inputs.
Balanced propagation delays: tpLH ∼− tpHL
Wide operating voltage range: VCC (opr) = 2 V to 5.5 V
Pin and function compatible with 74ALS165
TC74VHC165F
TC74VHC165FT
TC74VHC165FK
Weight
SOP16-P-300-1.27A: 0.18 g (typ.)
TSSOP16-P-0044-0.65A: 0.06 g (typ.)
VSSOP16-P-0030-0.50: 0.02 g (typ.)
Start of commercial production
1992-05
1 2014-03-01

1 Page





74VHC165 pdf, ピン配列
Timing Chart
CK
CK INH
Serial Input
Shift/ LOAD
A
B
C
Parallel
Inputs
D
E
F
G
H
Output QH
Output QH
TC74VHC165F/FT/FK
SERIAL SHIFT
H DON’T CARE UNTIL S/L GOES “L”
L
L
H
L
H
L
H
H LHLHLLH
L HLHLHHL
INHIBIT
LOAD
SERIAL SHIFT
3 2014-03-01


3Pages


74VHC165 電子部品, 半導体
Timing Requirements (input: tr = tf = 3 ns)
Characteristics
Symbol
Minimum pulse width
(CK, CK INH)
Minimum pulse width
( S/L )
Minimum set-up time
(PI- S/L )
Minimum set-up time
(SI-CK, CK INH)
Minimum set-up time
( S/L -CK, CK INH)
Minimum hold time
(PI- S/L )
Minimum hold time
(SI-CK, CK INH)
Minimum hold time
( S/L -CK, CK INH)
Minimum removal time
(CK INH-CK)
(CK-CK INH)
tw (L)
tw (H)
tw (L)
ts
ts
ts
th
th
th
trem
TC74VHC165F/FT/FK
Test Condition
VCC (V)
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
3.3 ± 0.3
5.0 ± 0.5
Ta =
25°C
Limit
6.0
4.0
7.5
5.0
7.5
5.0
5.0
4.0
5.0
4.0
0.5
1.0
0.0
0.5
0.0
0.5
Ta =
40 to
85°C
Limit
7.0
4.0
9.0
6.0
8.5
5.0
6.0
4.0
6.0
4.0
0.5
1.0
0.0
0.5
0.0
0.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
3.3 ± 0.3 5.0
5.0
ns
5.0 ± 0.5 3.5
3.5
6 2014-03-01

6 Page



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