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PDF MCM6665A Data sheet ( Hoja de datos )

Número de pieza MCM6665A
Descripción 64K DRAM
Fabricantes Motorola Semiconductors 
Logotipo Motorola Semiconductors Logotipo



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No Preview Available ! MCM6665A Hoja de datos, Descripción, Manual

® MOTOROLA
MCM6665A
64K BIT DYNAMIC RAM
The MCM6665A is a 65,536 bit, high-speed, dynamic Random-
Access Memory. Organized as 65,536 one-bit words' and fabricated
using HMOS high-performance N-channel silicon-gate technology, this
new breed of 5-volt only dynamic RAM combines high performance
with low cost and improved reliability.
By multiplexing row- and column-address inputs, the MCM6665A
requires only eight address lines and permits packaging in standard
16-pin dual-in-line packages. Complete address decoding is done on
chip with addr8ss latches incorporated. Data out is controlled by CAS
allowing for greater system flexibility.
All inputs and outputs, including clocks, are fully TTL compatible.
The MCM6665A incorporates a one-transistor cell design and dynamic
storage techniques.
• Organized as 65,536 Words of 1 Bit
• Single + 5 V Operation 10%)
• Full Power Supply Range Capabilities
• Maximum Access Time
MCM6665A 15= 150 ns
MCM6665A-20= 200 ns
• Low Power Dissipation
302.5 mW Maximum (Active) (MCM6665A-15)
22 mW Maximum (Standby)
• Three-State Data Output
• Internal Latches for Address and Data Input
• Early-Write Common I/O Capability
• 16K Compatible 128-Cycle, 2 ms Refresh
• RAS-only Refresh Mode
• CAS Controlled Output
• Upward Pin Compatible from the 16K RAM (MCM4116, MCM4517)
• Fast Page Mode Cycle Time
• Low Soft Error Rate <0.1 % per 1000 Hours (See Soft Error Testing)
BLOCK DIAGRAM
Precharge
~AD -.
Memory
Array
Al -.
A2 -.
A3 -.
A4 -.
A5 -.
A6 -.
A? -.
Ql
Ci.
E
~
!'"
0
~
co
:''Qg""l
«
Row Decoder
Memory
Array
Memory
Array
Row Decoder
Memory
IpreCharge
Array
Clock
Cil Memory
'0
8
Array
Ql
0
~ Row Decoder
(5
u Memory
Array
Memory
Cil Array
"D
§
0 Row Decoder
~
(5 Memory
u Array
>
* Refresh Function Available on MCM6664A
-Vec
-VSS
r--
~
~
~
u0 ~
.£:
'"Q)
"iii ~
a:
~ ~ Write,W
~~
0
U
g>
f+ Data In, D
E
~
~
~ Output
Data, Q
-
MOS
IN-CHANNEL, SILICON-GATE)
65,536-BIT
DYNAMIC RANDOM ACCESS
MEMORY
P SUFFIX
PLASTIC PACKAGE
CASE 648
PIN ASSIGNMENT
N/C
D
W
RAS
AO
A2
Al
VCC
VSS
CAS
Q
A6
A3
A4
A5
A?
AD-A?
D
Q
RAS
CAS
Vec
VSS
PIN NAMES
.. Address Input
... Data In
Data Out
Read/Write Input
Row Address Strobe
Column Address Strobe
. Power 1+5 V)
Ground
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it i~
advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high-
impedance circuit.
2-17
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MCM6665A pdf
MCM6665A
VIH-
RAS
VIL -
PAGE MODE READ CYCLE
~-------------------------tRAS--------------------------------~
VIH-
CAS VI, -
VIH-
Addresses
VIL -
VOH-
o IData Outl
VOL -
HI Z
RAS VIH-
VIL -
CAS VIH-
VIL -
PAGE MODE WRITE CYCLE
w VIH-
VIL-~~~~~~~-f-----1~~~~~~~-----i~~~~~f~~~~----~~~~~~~~
VIH-~~~f--7\.
D !Data Inl
VI L- - .......--I~ ~----------.=lf"
2-21
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MCM6665A arduino
FIGURE 24 - FUNCTIONAL BLOCK DIAGRAM
:1 lData·ln
Buffer
1
Pin 14
0
I tData Out
Buffer 1
1
1 of 2
Data and
Array Select
Row Address A?
I/O Bus
I/O Bus
r--
.... SA
B192
Bit Array
...
...+-I-- f-
DC
+-f-+
... DC
I+- .....
8192
Bit Array
...
SA fot-
Pin
w
;D--1 : 0 - + +3
R/W
Clocks
1 of 128
~ Row Decode I
10f128
~
FI Row Decode
~Pin
4
.. ... f+-'I\.) RAS
""J)- ... ....r() RAS
1-....J Clocks
~ SA
8192
Bit Array
DC <l>
"0
~
0
<D U
LNO O<l>
8192
DC
Bit Array
SA
- -1 -E'In '0
~-tc:Y .. .........CAS
CAS
Clocks
I
I
Col. Dec
Enable
~ SA
8192
Bit Array
DC +-
a- ::>
u
8192
DC Bit Array
SA ~
-Pin
1
r- ..REFRESH-
. , ~~• available
only ICM6664A
J Refresh
1 Clocks
...
1 of 128
Row Decode
t
...
.. 1 of 128
Row Decode
t
I ! I J LAdRde.fetr
Add
Clks
~ SA
8192
Bit Array
DC ~
~ DC
8192
Bit Array
SA ~
AO-A?
Internal
Row Addresses
IAO-A61
il
Pin Numbers
,,6,7,9,10,'-1,12,13
External
I.. Ext(lnt
'I Add. Mux ..
Ad~
,~~~~ I
r-",.
Pin8
Pin 16.
II VCC
II Vc:.<:,
L~V:JB- B
DRAM
s::
so::
0)
0)
0)
»(,J'I
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