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ICS95V860 の電気的特性と機能

ICS95V860のメーカーはIntegrated Circuit Systemsです、この部品の機能は「2.5V DDR/Zero Delay Fan Out Buffer」です。


製品の詳細 ( Datasheet PDF )

部品番号 ICS95V860
部品説明 2.5V DDR/Zero Delay Fan Out Buffer
メーカ Integrated Circuit Systems
ロゴ Integrated Circuit Systems ロゴ 




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ICS95V860 Datasheet, ICS95V860 PDF,ピン配置, 機能
Integrated
Circuit
Systems, Inc.
ICS95V8 6 0
2.5V DDR/Zero Delay Fan Out Buffer (100MHz - 225MHz)
Recommended Application:
DDR Memory Modules / Zero Delay Fan Out Buffer
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 13 differential clock distribution (SSTL_2)
• Feedback pins for input to output synchronization
• PD# for power management
• Spread Spectrum-tolerant inputs
• Auto PD when input signal removed
• 0°C to 85°C operation
Functionality
INPUTS
AVDD PD# CLK_INT
OUTPUTS
CLK_INC CLKT CLKC FB_OUTT FB_OUTC
PLL State
GND H
L
H LH L
H Bypassed/off
GND
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
H
L
H
H
X
HL
XX
LH
HL
<20MHz)
HL
ZZ
LH
HL
ZZ
H
Z
L
H
Z
L Bypassed/off
Z off
H on
L on
Z off
Switching Characteristics:
• CYCLE - CYCLE jitter (>100MHz):<75ps
• OUTPUT - OUTPUT skew: <70ps
• DUTY CYCLE: 49% - 51%
Block Diagram
PD#
I2C_SCL, I2C_SDA
I2C_A0, I2CA1
Control
Logic
FB_INT
FB_INC
CLK_INC
CLK_INT
PLL
0675D—01/07/04
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
CLKT10
CLKC10
CLKT11
CLKC11
CLKT12
CLKC12
Free Datasheet http://www.nDatasheet.com

1 Page





ICS95V860 pdf, ピン配列
ICS95V8 6 0
Pin Descriptions
PIN NUMBER
PIN NAME
B3, B4, B7, B8,
C10, D2, D10,
G10, H2, H10, K3,
K4, K7, K8
VDD
A11, B2, B5, B6,
B9, B10, C2, E10,
F10, J2, J10, K2,
K5, K6, K9, K10,
K11, L11
GND
F1 AVDD
F2
L10
A3, A5, A7, A9,
C11, E11, G11,
J11, L2, L4, L6,
L8, H1
A2, A4, A6, A8,
B11, D11, F11,
H11, L3, L5, L7,
L9, J1
AGND
VDD_I2C
CLKT(12:0)
CLKC(12:0)
G2 CLK_INC
G1 CLK_INT
D1 FB_OUTC
C1
E1
E2
A10
A1, B1
K1
L1
FB_OUTT
FB_INT
FB_INC
PD#
I2C_A0, I2C_A1
I2C_SDA
I2C_SCL
TYPE
PWR Power supply 2.5V
DESCRIPTION
PWR Ground
PWR
PWR
PWR
Analog power supply, 2.5V
Analog ground.
I2C VDD pin for I2C_SDA, SCL bias.
OUT "True" Clock of differential pair outputs.
OUT "Complementary" clocks of differential pair outputs.
IN
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
"Complementary" reference clock input
"True" reference clock input
"Complementary" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC.
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT.
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error.
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error.
Power Down. LVCMOS input
I2C address bits.
I2C bus data line.
I2C bus clock line.
General Description
ICS95V860 is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to thirteen
differential clock output pairs (CLKT[0:12], CLKC[0:12]) and one differential clock output feedback pair (FB_OUT,
FB_OUTC).The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,
FB_INC) the input (PD#) and the Analog Power input (AVDD).When input (PD#) is low while power is applied, the receivers
are disabled, the PLL is turned off and the differential clock outputs are Tri-Stated. When AVDD is grounded, the PLL
is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL (appproximately 20MHz), the device will enter
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low.When
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and
outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input
clock pair (CLK_INC, CLK_INT).
0675D—01/07/04
(continued)
3
Free Datasheet http://www.nDatasheet.com


3Pages


ICS95V860 電子部品, 半導体
ICS95V8 6 0
Timing Requirements
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN MAX
Input clock frequency
freqop
100 225
Input clock duty cycle
dtin
40 60
UNITS
MHz
%
CLK stabilization
TSTAB
10 µs
Switching Characteristics
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITION
MIN
Low-to high level
propagation delay time
tPLH1
CLK_IN to any output
High-to low level propagation
delay time
tPLL1
CLK_IN to any output
Output enable time
tEN PD# to any output
Output disable time
tdis PD# to any output
Period jitter
Tjit (per)
-75
Half-period jitter
t(jit_hper)
-70
Input clock slew rate
tsl(i)
1
Output clock slew rate
Cycle to Cycle Jitter1
tsl(o)
Tcyc-Tcyc
1
-75
Static phase offset
tspo
-75
Output to Output Skew
Duty cycle
Tskew
DC2
49
TYP
5.5
5.5
5
5
0
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, where
the cycle (tc) decreases as the frequency goes up.
MAX UNITS
ns
ns
ns
ns
75 ps
70 ps
4 V/ns
2.5 V/ns
75 ps
75 ps
70 ps
51 %
0675D—01/07/04
6
Free Datasheet http://www.nDatasheet.com

6 Page



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部品番号部品説明メーカ
ICS95V860

2.5V DDR/Zero Delay Fan Out Buffer

Integrated Circuit Systems
Integrated Circuit Systems


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