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95V857 の電気的特性と機能

95V857のメーカーはIntegrated Circuit Systemsです、この部品の機能は「 ICS95V857」です。


製品の詳細 ( Datasheet PDF )

部品番号 95V857
部品説明 ICS95V857
メーカ Integrated Circuit Systems
ロゴ Integrated Circuit Systems ロゴ 




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95V857 Datasheet, 95V857 PDF,ピン配置, 機能
Integrated
Circuit
Systems, Inc.
ICS95V8 5 7
2.5V Wide Range Frequency Clock Driver (45MHz - 233MHz)
Recommended Application:
• DDR Memory Modules / Zero Delay Board Fan Out
• Provides complete DDR registered DIMM solution
with ICSSSTVF16857, ICSSSTVF16859 or
ICSSSTV32852
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 10 differential clock distribution (SSTL_2)
• Feedback pins for input to output synchronization
• PD# for power management
• Spread Spectrum-tolerant inputs
• Auto PD when input signal removed
Specifications:
• Meets PC3200 Class A+ specification for DDR-I 400
support
• Covers all DDRI speed grades
Switching Characteristics:
• CYCLE - CYCLE jitter: <50ps
• OUTPUT - OUTPUT skew: <40ps
• Period jitter: ±30ps
Pin Configuration
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
GND
CLKC2
CLKT2
VDD
VDD
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 GND
47 CLKC5
46 CLKT5
45 VDD
44 CLKT6
43 CLKC6
42 GND
41 GND
40 CLKC7
39 CLKT7
38 VDD
37 PD#
36 FB_INT
35 FB_INC
34 VDD
33 FB_OUTC
32 FB_OUTT
31 GND
30 CLKC8
29 CLKT8
28 VDD
27 CLKT9
26 CLKC9
25 GND
48-Pin TSSOP/TVSOP
6.10 mm Body, 0.50 mm Pitch = TSSOP
4.40 mm Body, 0.40 mm Pitch = TVSOP
Block Diagram
Functionality
INPUTS
OUTPUTS
PLL State
AVDD PD# CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC
GND H
L
H LH L
H Bypassed/off
GND
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
2.5V
(nom)
H
L
L
H
H
X
HL
LH
HL
LH
HL
<20MHz)(1)
HL
ZZ
ZZ
LH
HL
ZZ
H
Z
Z
L
H
Z
L Bypassed/off
Z off
Z off
H on
L on
Z off
PD#
FB_INT
FB_INC
CLK_INC
CLK_INT
Control
Logic
PLL
0674U01/27/09
FB_OUTT
FB_OUTC
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
Free Datasheet http://www.nDatasheet.com

1 Page





95V857 pdf, ピン配列
ICS95V8 5 7
Pin Descriptions
PIN NAME
TYPE
DESCRIPTION
VDD
PWR Power supply, 2.5V
GND
AVDD
AGND
CLKT(9:0)
CLKC(9:0)
CLK_INC
CLK_INT
FB_OUTC
FB_OUTT
FB_INT
FB_INC
PD#
PWR Ground
PWR
PWR
OUT
Analog power supply, 2.5V
Analog ground
"True" Clock of differential pair outputs
OUT "Complementary" clocks of differential pair outputs
IN "Complementary" reference clock input
IN
OUT
OUT
IN
IN
IN
"True" reference clock input
"Complementary" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error
"Complementary" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error
Power Down. LVCMOS input
This PLL Clock Buffer is designed for a VDD of 2.5V, an AVDD of 2.5V and differential data input and output levels.
The ICS95V857 is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT,
FB_OUTC).The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,
FB_INC), the 2.5-V LVCMOS input (PD#) and the Analog Power input (AVDD).When input (PD#) is low while power is
applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are tri-stated. When AVDD
is grounded, the PLL is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low.When
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and
outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input
clock pair (CLK_INC, CLK_INT).
The PLL to the ICS95V857 clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC) provide high-performance, low-skew, low-jitter, output differential clocks (CLKT[0:9], CLKC[0:9]). The
ICS95V857 is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
The ICS95V857 is characterized for operation from 0°C to 85°C, and will meet JEDEC Standard 82-1 and 82-1A Class
A+ for registered DDR clock drivers.
0674U01/27/09
3
Free Datasheet http://www.nDatasheet.com


3Pages


95V857 電子部品, 半導体
ICS95V8 5 7
Timing Requirements
TA = 0 - 85°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN MAX
Max clock frequency
freqop
2.5V+0.2V @ 25oC
45 233
Application Frequency
Range
freqApp
2.5V+0.2V @ 25oC
95 220
Input clock duty cycle
dtin
40 60
UNITS
MHz
MHz
%
CLK stabilization
TSTAB
15 µs
Switching Characteristics (see note 3)
PARAMETER
SYMBOL
CONDITION
MIN TYP
Low-to high level
propagation delay time
tPLH1
CLK_IN to any output
3.5
High-to low level propagation
delay time
tPLL1
CLK_IN to any output
3.5
Output enable time
Output disable time
tEN PD# to any output
tdis PD# to any output
3
3
Period jitter
Half-period jitter
Tjit (per)
t(jit_hper)
100MHz to 200MHz
100MHz to 200MHz
-30
-75
Input clock slew rate
tsl(i)
1
Output clock slew rate
tsl(o)
1
Cycle to Cycle Jitter1
Tcyc-Tcyc 100MHz to 200MHz
-50
Static Phase Offset
t(static
phase
4
offset)
-50
Output to Output Skew
Tskew
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies.This is due to the formula: duty cycle=twH/tc, where
the cycle (tc) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
0
MAX UNITS
ns
ns
ns
ns
30 ps
75 ps
4 V/ns
2 V/ns
50 ps
50 ps
40 ps
0674U01/27/09
6
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6 Page



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部品番号部品説明メーカ
95V857

ICS95V857

Integrated Circuit Systems
Integrated Circuit Systems


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