DataSheet.jp

HI-6120 の電気的特性と機能

HI-6120のメーカーはHolt Integrated Circuitsです、この部品の機能は「(HI-6120 / HI-6121) MIL-STD-1553 Remote Terminal ICs」です。


製品の詳細 ( Datasheet PDF )

部品番号 HI-6120
部品説明 (HI-6120 / HI-6121) MIL-STD-1553 Remote Terminal ICs
メーカ Holt Integrated Circuits
ロゴ Holt Integrated Circuits ロゴ 




このページの下部にプレビューとHI-6120ダウンロード(pdfファイル)リンクがあります。

Total 30 pages

No Preview Available !

HI-6120 Datasheet, HI-6120 PDF,ピン配置, 機能
November, 2015
HI-6120 Parallel Bus Interface and
HI-6121 Serial Peripheral Interface (SPI)
MIL-STD-1553 Remote Terminal ICs
GENERAL DESCRIPTION
The HI-6120 and HI-6121 provide a complete, integrated,
3.3V MIL-STD-1553 Remote Terminal in a monolithic sili-
con gate CMOS device. Two host interface options are
offered: The HI-6120 uses a 16-bit parallel host bus inter-
face for access to registers and RAM and is offered in a
100-pin plastic quad flat pack (PQFP). The HI-6121 has
a 4-wire SPI (Serial Peripheral Interface) host connection
and comes in a reduced pin count 52-pin PQFP or 9mm
x 9mm 64-pin QFN. Both devices handle all aspects of
the MIL-STD-1553 protocol, including message encod-
ing, decoding, error detection, illegal command detection
and data buffering. Host data management is simplified
by storing message information and data within the on-
chip 32K x 16 static RAM.
A descriptor table in shared RAM provides fully program-
mable memory management. Multiple descriptor tables
can be implemented for fast context switching. Trans-
mit and receive commands can use any of four differ-
ent data buffer modes: indexed (single) buffering, ping-
pong (double) buffering or two circular buffer schemes.
Transmit and receive commands for each subaddress
may use different buffer modes. Mode code commands
employ a simple scheme for storing mode data and mes-
sage information with programmable interrupts.
The device provides internal illegalization capability,
allowing any subset of subaddress, command T/R bit,
broadcast vs non-broadcast and word count (or mode
code) to be illegalized, resulting in a total of 4,096 pos-
sible combinations. The illegalization table resides in in-
ternal RAM. The RT can also operate without illegal com-
mand detection, providing “in form” responses to all valid
commands. Broadcast command recognition is optional.
The HI-6120 and HI-6121 provide programmable inter-
rupts for automatic message handling, message status
and general status. A host interrupt history log maintains
information about the last 16 interrupts.
The HI-6120 and HI-6121 can be configured for automat-
ic self-initialization. A dedicated SPI port reads data from
external serial EEPROM memory to fully configure the
descriptor table, illegalization table and host interrupts.
Internal dual-redundant transceivers provide direct
connection to bus isolation transformers. The device
is offered with industrial temperature range as well as
extended temperature range with optional burn-in. A
“RoHS compliant” lead-free option is also offered.
FEATURES
Fully integrated 3.3V Remote Terminal meets all
requirements for MIL-STD-1553B Notice 2
Four data buffer modes for subaddress transmit
and receive commands. Data buffer modes are
independently selectable for transmit and receive
commands on each subaddress
• Simplified mode code command handling
Integral 16-bit Time-Tag counter has programma-
ble options for clock, interrupts and auto-synchro-
nization
Message information and time-tag words are
stored with message data words for all transacted
messages
In compliance with MIL-STD-1553B Notice 2, re-
ceived data from broadcast messages may be
optionally separated from non-broadcast received
data
Optional interrupt log buffer stores the most recent
16 interrupts to minimize host service duties
Optional illegal command detection uses internal
table
Optional automatic self-initialization at reset
±8kV ESD Protection (HBM, all pins)
MIL-STD-1760 compliant
PIN CONFIGURATION (TOP)
COMP - 1
CE - 2
MODE - 3
SI - 4
SCK - 5
SO - 6
MCLK - 7
RTA0 - 8
RTA1 - 9
RTA2 - 10
MR - 11
RTA3 - 12
RTA4 - 13
HI-6121PQx
HI-6121 in
PQFP-52 Package
39 - TEST
38 - LOCK
37 - MTSTOFF
36 - BUSA
35 - VCCP
34 - BUSA
33 - BUSB
32 - VCCP
31 - BUSB
30 - TEST0
29 - TEST3
28 - TEST2
27 - TEST1
DS6120 Rev. I
HOLT INTEGRATED CIRCUITS
www.holtic.com
1
11/15

1 Page





HI-6120 pdf, ピン配列
HI-6120, HI-6121
Table of Contents
1. BLOCK DIAGRAM............................................................................................ 10
2. PIN DESCRIPTIONS........................................................................................ 11
3. FUNCTIONAL OVERVIEW............................................................................... 16
3.1. Shared RAM Utilization............................................................................................... 16
3.1.1. Descriptor Table........................................................................................................... 16
3.1.2. Illegalization Table........................................................................................................ 16
3.1.3. Message Data Buffers.................................................................................................. 16
3.1.4. Storage for Mode Code Commands............................................................................ 16
3.1.5. Interrupt Log................................................................................................................. 17
3.2. Hardware Feature Summary....................................................................................... 17
3.2.1. Clock Interrupts............................................................................................................ 17
3.2.2. Remote Terminal Address Inputs................................................................................. 17
3.2.3. Integral Time-Tag Counter........................................................................................... 17
3.2.4. Dual Bus Transceivers................................................................................................. 17
3.2.5. Encoder and Decoders................................................................................................ 17
3.2.6. Auto-Initialization Serial EEPROM Interface................................................................ 17
4. MEMORY AND REGISTER ADDRESSING...................................................... 18
5. REGISTERS...................................................................................................... 20
5.1. Configuration Register 1 (0x0000)............................................................................ 21
5.2. Configuration Register 2 (0x0001)............................................................................ 24
5.3. Operational Status Register (0x0002)....................................................................... 28
5.4. Current Command Register (0x0003)....................................................................... 30
5.5. Current Control Word Address Register (0x0004)..................................................... 31
5.6. Descriptor Table Base Address Register (0x0005) ................................................... 31
5.7. Pending Interrupt Register (0x0006)......................................................................... 31
5.8. 1553 Status Word Bits Register (0x0007)................................................................. 33
5.9. Time-Tag Register (0x0008)...................................................................................... 35
5.10. Interrupt Log Address Register (0x0009).................................................................. 35
5.11. Current Message Information Word Address Register (0x000A).............................. 36
5.12. Memory Address Pointer Register (HI-6121 only) (0x000F) ................................... 36
5.13. Interrupt Enable Register (0x0010)........................................................................... 37
HOLT INTEGRATED CIRCUITS
3


3Pages


HI-6120 電子部品, 半導体
HI-6120, HI-6121
17. ELECTRICAL CHARACTERISTICS............................................................... 147
17.1. Absolute Maximum Ratings....................................................................................... 147
17.2. Recommended Operating Conditions....................................................................... 147
17.3. DC Electrical Characteristics..................................................................................... 147
17.4. AC Electrical Characteristics ― HI-6121 Host Bus Interface Timing........................ 148
17.5. AC Electrical Characteristics ― HI-6120 Host Bus Interface Timing........................ 149
18. MIL-STD-1553 BUS INTERFACE................................................................... 154
19. RECOMMENDED TRANSFORMERS............................................................ 155
20. THERMAL CHARACTERISTICS.................................................................... 155
21. ADDITIONAL PIN / PACKAGE CONFIGURATIONS...................................... 156
21.1. HI-6121PCx (64-pin QFN)......................................................................................... 156
21.2. HI-6120PQx (100-pin PQFP).................................................................................... 157
22. ORDERING INFORMATION........................................................................... 158
23. REVISION HISTORY...................................................................................... 159
24. PACKAGE DIMENSIONS............................................................................... 161
HOLT INTEGRATED CIRCUITS
6

6 Page



ページ 合計 : 30 ページ
 
PDF
ダウンロード
[ HI-6120 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
HI-6120

(HI-6120 / HI-6121) MIL-STD-1553 Remote Terminal ICs

Holt Integrated Circuits
Holt Integrated Circuits
HI-6121

(HI-6120 / HI-6121) MIL-STD-1553 Remote Terminal ICs

Holt Integrated Circuits
Holt Integrated Circuits


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap