|
|
PDF AR8032 Data sheet ( Hoja de datos )
| Número de pieza | AR8032 | |
| Descripción | Integrated 10/100 Fast Ethernet Transceiver | |
| Fabricantes | Atheros | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AR8032 (archivo pdf) en la parte inferior de esta página. Total 52 Páginas | ||
|
No Preview Available !
Data Sheet
July 2010
AR8032 Integrated 10/100 Fast Ethernet Transceiver
General Description
The Atheros AR8032 Fast Ethernet transceiver
is a highly integrated physical layer device that
transmits and receives high-speed data over
standard category 5 (CAT 5) unshielded
twisted pair cable.
The AR8032 is compliant with 100 BASE-TX
and 10 BASE-T IEEE 802.3 standards. The
AR8032 device uses advanced mixed-signal
processing technology and integrates functions
such as adaptive equalization, and timing
recovery to deliver substantial power savings
and operation in noisy environments.
The AR8032 device supports the Media
Independent Interface (MII) and Reduced
Media Independent Interface (RMII) for direct
connection to a Fast Ethernet-capable MAC.
The AR8032 supports the Atheros Cable
Diagnostic Test (CDT) feature, which uses Time
Domain Reflectometry (TDR) technology to
quickly and remotely identify potential cable
malfunctions without deploying field support
personnel or bringing down the network. The
AR8032 solution detects and reports issues
such as PHY malfunctions, bad/marginal cable
or patch cord segments or connectors, thus
significantly reducing installation time, cable
debug efforts, and overall network support
cost.
Manufactured in a standard CMOS process, the
AR8032 is packaged in a 32-pin QFN, featuring
a small body size of 5 x 5mm.
Features
n 10/100 BASE-T IEEE 802.3 compliant
n Supports MII/RMII interface
n Low power modes with internal automatic
DSP power saving scheme
n Fully integrated digital adaptive equalizers
All digital baseline wander correction
n Supports external 25 MHz clock source in
MII mode
n Supports external 50 MHz clock source in
RMII mode
n Automatic speed downshift mode
n Automatic MDI/MDIX crossover
n Automatic polarity correction
n Loopback modes for diagnostics
n IEEE 802.3u compliant Auto-Negotiation
n Software programmable LED modes
n Cable Diagnostic Test (CDT)
n Requires only one 3.3V power supply
n 32-pin QFN 5mm x 5 mm package
AR8032 Functional Block Diagram
DAC
MDIP/
AGC
N[0:1]
Feed
PGA ADC Forward
Equalizer
PMA
Timing & Phase
Recovery
Symbol
Encoder
MII/
RMII
Tx
Decision
Feedback
Equalizer
Symbol
Decoder /
Alignment
MII/
RMII
Rx
Auto -
Negotiation
MII Management
Registers
DLL
© 2010 by Atheros Communications, Inc. All rights reserved. Atheros®, Atheros Driven®, Atheros XR®, Driving the Wireless Future®, ROCm®, Super A/G®, Super G®,
Super N®, Total 802.11®, XSPAN®, Wireless Future. Unleashed Now.®, and Wake on Wireless® are registered by Atheros Communications, Inc. Atheros SST™, Signal-
Sustain Technology™, the Air is Cleaner at 5-GHz™, and 5-UP™ are trademarks of Atheros Communications, Inc. The Atheros logo is a registered trademark of Atheros
Communications, Inc. All other trademarks are the property of their respective holders. Subject to change without notice.
COMPANY CONFIDENTIAL
•1
Free Datasheet http://www.nDatasheet.com
1 page  
1. Pin Descriptions
This section contains a package pinout for the
AR8032 QFN 32pin and a listing of the signal
descriptions (see Figure 1-1).
The following nomenclature is used for signal
names:
NC No connection to the internal die
is made from this pin
_# At the end of the signal name,
indicates active low signals
P Power
The following nomenclature is used for signal
types described in Table 1-1:
D Open drain
IA Analog input
I Digital input
IH Digital input with histeresis
I/O Digital input/output
OA Analog output
O Digital output
PD Internal pull-down for digital
input
PU Internal pull-up for digital input
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8032 Integrated 10/100 Mbps Ethernet Transceiver • 5
July 2010 • 5
Free Datasheet http://www.nDatasheet.com
5 Page 
2.3 Loopback Modes
2.3.1 Digital Loopback
Digital loopback provides the ability to loop
transmitted data back to the receiver using
digital circuitry in the AR8032 device.
Figure 2-2 shows a block diagram of digital
loopback.
MAC/
Switch
RGMII
PHY
Digital
PHY
AFE
Figure 2-2. Digital Loopback
2.3.2 External Cable Loopback
External cable loopback loops MII Tx to MII Rx
through a complete digital and analog path
and an external cable, thus testing all the
digital data paths and all the analog circuits.
Figure 2-3 shows a block diagram of external
cable loopback.
MAC/
Switc
h
PH
MII
PHY
Digital
Y
AF
E
Figure 2-3. External Cable Loopback
2.3.3 Cable Diagnostic Test
The Cable Diagnostic Test (CDT) feature in the
AR8032 device uses Time Domain
Reflectometry (TDR) to identify remote and
local PHY malfunctions, bad/marginal cable or
patch cord segments, or connectors. Some of
the possible problems that can be diagnosed
include opens, shorts, cable impedance
mismatch, bad connectors, termination
mismatch, and bad magnetics. The CDT can be
performed when there is no link partner or
when the link partner is auto-negotiating.
2.3.4 LED Interface
The LED interface can either be controlled by
the PHY or controlled manually, independent
of the state of the PHY. Two status LEDs are
available. These can be used to indicate
operation speed, and link status. The LEDs can
be programmed to different status functions
from their default value. They can also be
controlled directly from the MII register
interface.
2.3.5 Power Supplies
The AR8032 device requires only one power
supply: 3.3V.
2.3.6 Low Power Modes
The AR8032 device supports the software
power-down low power mode. The standard
IEEE power-down mode is entered by setting
the POWER_DOWN bit (bit [11]) of the register
“Control Register” on page 22 equal to one.
In this mode, the AR8032 device ignores all
MAC interface signals except the MDC/MDIO.
It does not respond to any activity on the CAT
5 cable. The device cannot wake up on its own.
It can only wake up by setting the
POWER_DOWN bit (bit [11]) of the register
“Control Register” on page 22” to 0.
2.3.7 Hibernation Mode
The AR8032 device supports hibernation
mode. When the cable is unplugged, the
AR8032 will enter hibernation mode after
about 10 seconds. The power consumption in
this mode is very low compared to the normal
mode of operation. When the cable is re-
connected, the AR8032 wakes up and normal
functioning is restored.
Atheros Communications, Inc.
COMPANY CONFIDENTIAL
AR8032 Integrated 10/100 Mbps Ethernet Transceiver • 11
July 2010 • 11
Free Datasheet http://www.nDatasheet.com
11 Page | ||
| Páginas | Total 52 Páginas | |
| PDF Descargar | [ Datasheet AR8032.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AR8030 | Integrated 10/100/1000 Mbps Ethernet Transceiver |  Atheros Communications |
| AR8031 | Integrated 10/100/1000 Mbps Ethernet Transceiver | Atheros Communications |
| AR8032 | Integrated 10/100 Fast Ethernet Transceiver | Atheros |
| AR8035 | Integrated 10/100/1000 Gigabit Ethernet Transceiver | Atheros |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |